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IXP400 Software
Access-Layer Components: DMA Access Driver (IxDmaAcc) API
April 2005 IXP400 Software Version 2.0 Programmer’s Guide
128 Document Number: 252539, Revision: 007
• Burst mode is not supported for DMA targets at AHB South Bus. This is due to hardware
restriction. Therefore, all DMA transactions originated or designated the south AHB bus
peripherals is carried out in single transaction mode.
• The DMA access component is fully tested on SDRAM and flash devices only. Even though
the IxDmaAcc is designed to provide capability to offload large data transfers between
peripherals in the IXP4XX product line and IXC1100 control plane processors’ memory map.
• These DMA restrictions apply when a flash is a destination device:
— Burst mode is not supported and only supports single mode.
— Incremental source to fixed destination DMA addressing mode is not supported.
— DMA transfer width for the destination must match the flash device data bus width.
— Byte-reverse DMA mode with fixed source to incremental destination is not supported
with the Flash write buffer mode.
• These DMA restrictions apply when a flash is a source device:
— Copy and clear DMA mode is not supported
— DMA transfer width for the source must match the Flash device data bus width.
8.11 Error Handling
IxDmaAcc returns an error type to the user when the client is expected to handle the error. Internal
errors will be reported using standard IXP4XX product line and IXC1100 control plane processors
error-reporting techniques, such as the OSAL layer’s error-reporting mechanism.
8.12 Little Endian
This component does not work in little-endian mode, nor will codelets that utilize this component.