Intel IXP400 Frozen Dessert Maker User Manual


 
Intel
®
IXP400 Software
Access-Layer Components: ATM Manager (IxAtmm) API
Programmer’s Guide IXP400 Software Version 2.0 April 2005
Document Number: 252539, Revision: 007 77
5.7 Dependencies
IxAtmm configures the IXP4XX product line and IXC1100 control plane processors’ UTOPIA
Level-2 device through an interface provided by the IxAtmdAcc component.
IxAtmm is also responsible for configuring VC registrations with the IxAtmSch demo ATM
scheduler component and relaying CAC decisions to the client in the event of VC registration
failure.
IxAtmm is responsible for port traffic shaping by conveying traffic and scheduling information
between the ATM scheduler component and the cell transmission control interface provided by the
IxAtmdAcc component.
5.8 Error Handling
IxAtmm returns an error type to the user when the client is expected to handle the error. Internal
errors will be reported using the IXP4XX product line and IXC1100 control plane processors’
standard error-reporting techniques.
The established state of the IxAtmm component (registered ports, VCs, etc.) is not affected by the
occurrence of any error.
5.9 Management Interfaces
No management interfaces are supported by the IxAtmm component. If a management interface is
required for the ATM layer, the IxAtmm is the logical place for this interface to be implemented, as
the component is intended to provide an abstract public interface to the non-data path ATM
functions.
5.10 Memory Requirements
IxAtmm code is approximately 26 Kbytes in size.
IxAtmm data memory requirement — under peak cell-traffic load — is approximately 20 Kbytes.
Figure 24. Component Dependencies of IxAtmm
IxAtmm
IxAtmSch IAtmDAcc
B2294-01