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IXP400 Software
Access-Layer Components: Queue Manager (IxQMgr) API
April 2005 IXP400 Software Version 2.0 Programmer’s Guide
270 Document Number: 252539, Revision: 007
mechanism, although the choice of implementation would depend upon the OS, the application,
and the nature of the traffic. The following includes factors to be considered in selecting the
appropriate mechanism:
• Event-based interrupt – Interrupt driven through QM1 or QM2 interrupt:
— system is interrupted only when there is traffic to service
— suitable for low traffic rates
— provides lowest latency
• Timer-based interrupt – polled from timer-based interrupt:
— suitable for high traffic rates
— minimizes the ISR overhead
— most efficient use of the Intel XScale core
• Polling mode – Busy loop to poll the queues:
— suitable for higher traffic rates
— throttles traffic automatically when additional cycles are not available on the Intel XScale
core
The status flag gets cleared within the dispatcher loop prior to servicing of the callback function.
The QM1 and QM2 interrupt gets cleared when all the status flags for all the queues are cleared
and if the interrupt enable bit is set. There can only be one dispatcher loop that can be defined for
each set of queues.
Once the IxQMgr is initialized and the queues are configured, the Codelet/Customer code must
determine how to invoke the dispatcher. Prior to invoking the dispatcher function, as stated before,
the ixQMgrDispatcherLoopGet(&dispatcher), returns a function pointer for the
appropriate dispatcher. The dispatcher is invoked with an argument that points to the upper or
lower 32 queues to determine if any queues in that group require servicing.
Note: Only one dispatcher can be invoked per each set of upper and lower 32 queues. The client can
register multiple callbacks as long as each of the callbacks are for different queues. When
interrupted, the dispatcher will read the status flag register from the AQM and service only one of
the callbacks that was registered for a given queue. In the event that multiple callbacks are
registered for the same queue, the dispatcher will service the last registered callback.
Figure 90 shows the following sequence of events that occur when a dispatcher is run in the context
of an interrupt.
At the start of the dispatcher, the interrupt register is read and written back immediately except in
case of a livelock dispatcher. Since livelock prevention uses sticky interrupt, the interrupt gets
cleared only when the queue threshold falls below the set watermark level.
1. The user registers a callback function with the access-layer component (for example, EthAcc).
The dispatcher invokes callback in the access-layer component, and the access-layer
component then invokes the user callback.
2. When the NPE receives a packet it updates the Rx Queue with location of the buffer.
3. Provided the Interrupt bit is set, when the water mark is crossed the status flag gets updated
corresponding to that queue and it triggers an interrupt to the Intel XScale core.
4. The Intel XScale core vectors the interrupt to the corresponding ISR.