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IXP400 Software
Access-Layer Components: Ethernet Access (IxEthAcc) API
Programmer’s Guide IXP400 Software Version 2.0 April 2005
Document Number: 252539, Revision: 007 131
9.3.2 Queue Manager
The AHB Queue Manager is a hardware block that communicates buffer pointers between the NPE
cores and the Intel XScale core. The IxQMgr API provides the queuing services to the access-layer
and other upper level software executing on the Intel XScale core. The primary use of these
interfaces is to communicate the existence and location of network payload data and Ethernet
service configuration information in external SDRAM.
Ethernet frames are presented to an Ethernet-capable NPE via its Ethernet coprocessor, which
serves as an interface between the Ethernet MAC and the NPE core block. Ethernet frame payloads
are transferred from the Ethernet coprocessor to the host NPE in discrete blocks of data. The
frames are buffered in NPE internal data memory, optionally filtered according to their destination
MAC address, checked for errors, and then (assuming that no errors exist and that the frame is not
filtered) transferred to external SDRAM. The Intel XScale core client (via IxEthAcc) is notified of
the arrival of new frames via the queue manager interface.
9.3.3 Learning/Filtering Database
IxEthAcc relies on the IxEthDB component for the MAC learning and filtering required in a
routing or bridging application.
The NPEs provide a function whereby MAC address-source learning is performed on received
(ingress) Ethernet frames. Not all NPE microcode images provide the filtering capability. If source
learning is enabled, the source MAC addresses are automatically populated in a learning database.
For a frame to be filtered, there must be a filtering database entry whose MAC address matches the
frame’s destination MAC address and whose port ID matches that of the ingress MAC.
Each entry in the filtering database is composed of a MAC address and a logical port number.
Whenever the bridge receives a frame, the frame is parsed to determine the destination MAC
address, and the filtering database is consulted to determine the port to which the frame should be
forwarded. If the destination MAC address of the frame being processed has been learned on the
same interface from which it was received, it is dropped. Otherwise, the frame is forwarded from
the NPE to the Intel XScale core.
9.3.4 MAC/PHY Configuration
IxEthMii is used primarily to manipulate a minimum number of necessary configuration registers
on Ethernet PHYs supported on the Intel
®
IXDP425 / IXCDP1100 Development Platform, the
Coyote* Gateway Reference Design, and the Intel
®
IXDP465 Development Platform, without the
support of a third-party operating system. Codelets and software used for Intel internal validation
are the consumers of this API, although it is provided as part of the IXP400 software for public use.
While the MAC configuration is performed within IxEthAcc, the PHY configuration requires both
IxEthAcc and IxEthMii. Since the MAC also controls the MDIO interface that is used for
configuring the PHY, IxEthMii must initialize the MAC in order for the PHY to be configured.
IxEthAcc initializes the MAC and virtual memory mapping and executes all register reads/writes
on the PHY. IxEthMii provides the register definitions for supported PHYs. Thus, IxEthMii and
IxEthAcc are dependant upon each other.