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IXP400 Software
Access-Layer Components: Parity Error Notifier (IxParityENAcc) API
April 2005 IXP400 Software Version 2.0 Programmer’s Guide
234 Document Number: 252539, Revision: 007
For the purposes of this document, the following terms will be used as defined below.
Error Correction Logic/Error Correction Code
The Error Correction Logic in the Memory Controller Unit (MCU) generates the ECC code (which
requires additional bits for the code word) for DDR SDRAM reads and writes. For reads, this logic
compares the ECC code read with the locally generated ECC code. If the codes do not match, then
the Error Correction Logic determines the error type. For a single-bit error, this block determines
which bit resulted in the error and corrects the error before the data is presented onto the bus.
However, the error still remains in the memory location and needs to be fixed by writing the
corrected data to the memory location. For writes, ECC logic in the MCU generates the ECC and
sends it with the data to the memory.
Scrubbing/Memory Scrub
Scrubbing is the process of correcting an error in a memory location. When the MCU detects an
error during a read, the MCU logs the address where the error occurred and interrupts the Intel
XScale core. The Intel XScale core must then write back to the memory location to fix the error
through a software handler. Note that the scrub rectifies only single-bit parity errors detected by the
DDR MCU.
Parity Error Context
This refers to the type of the parity error, the source of the parity error (i.e., the block which has the
parity error) and the address of the failed word where applicable. The IxParityENAcc API provides
a Parity Error Context to the client application when a parity or ECC error is detected.
Parity and Error Correction Code
Parity error detection is a simple and reliable mechanism to detect a single-bit error in a memory
location. In general this mechanism is implemented by using an additional single bit along with the
data bits in a memory location so that the bits set are of even/odd number and there is an even/odd
number of ‘1’s in the memory location. The MCU hardware will also detect multiple bit errors, but
cannot detect whether the MCU is configured for odd or even parity.
16.2.2 Parity and ECC Capabilities in the
Intel
®
IXP45X and Intel
®
IXP46X Product Line
The IXP46X network processors can detect a variety of parity or ECC errors. The individual
hardware blocks raise an interrupt to notify the Intel XScale core about these failures. The interrupt
controller on IXP46X network processors has a set of interrupts classified as ‘error’ class. These
interrupts take unconditional high-priority from the normal positional priority interrupts. This
section summarizes the interrupt behavior as it applies when a parity or ECC error is detected.
Note: For detailed information regarding the specific parity and ECC capabilities and interrupt
mechanisms of IXP46X network processors, refer to the Intel
®
IXP46X Product Line of Network
Processors Developer’s Manual.
16.2.2.1 Network Processing Engines
The NPE will lock and cease to operate immediately when affected by a parity error in its internal
memories or due to external errors in coprocessors (AHB Coprocessor, or Switching Coprocessor).
External NPE ports will be disabled. An interrupt is sent to the Intel XScale core through the
interrupt controller, and the parity context will provide information on whether the interrupt is
related to internal memory parity errors or an external coprocessor error.