Filter
Top Products
Intel
®
IXP400 Software
Endianness in Intel
®
IXP400 Software
Programmer’s Guide IXP400 Software Version 2.0 April 2005
Document Number: 252539, Revision: 007 355
— Performance Monitoring Unit
— Interrupt Controller
— GPIO Controller
— Timer Block
—SSP, I
2
C and IEEE 1588 units on the IXP46X product line.
• Blocks controlled by IXP400 software:
— NPE Message Handler and Execution control registers
— Ethernet MAC control
— Universal Serial Bus (USB)
The APB peripherals are placed in Address Coherent mode to nullify changes from the existing
Big-Endian BSP.
27.5.2 AHB Memory-Mapped Registers
There are several other memory-mapped areas within the processors:
• AHB Queue Manager. The configuration is covered in the “Queue Manager — IxQMgr” on
page 355.
• PCI. Further details are provided in “PCI” on page 361.
— Control registers. These registers are all word-wide (32 bits) and operate in Address
Coherent Little-Endian mode.
— PCI memory (AHB mapped, 0x48xx,xxxx Phy space). This space must be mapped Data
Coherent.
• Expansion Bus registers. These registers are all word-wide (32 bits) and operate in Address
Coherent Little-Endian mode.
• SDRAM control registers. These registers are all word-wide (32 bits) and operate in Address
Coherent Little-Endian mode.
27.5.3 Intel
®
IXP400 Software Core Components
IXP400 software contains several structural components used by all other IXP400 software access-
layer components. All of the software components are otherwise referred to as the Access-Layer
and provide software interfaces for control of the various hardware blocks within the processor.
Note: Changes to ixEthAcc listed here are indicative of the types of changes required in other
components.
27.5.3.1 Queue Manager — IxQMgr
The NPE Queue Manager component provides the interface to the hardware queue manager block.
All registers and hardware FIFOs are word-wide (32 bits). Data Coherent Little-Endian mode is
used.