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IXP400 Software
Access-Layer Components: HSS-Access (IxHssAcc) API
April 2005 IXP400 Software Version 2.0 Programmer’s Guide
204 Document Number: 252539, Revision: 007
13.5.3 Channelized Disconnect
When the channelized service is not needed any more on a particular HSS port,
ixHssAccChanPortDisable() is called to stop the channelized service on that port, then
ixHssAccChanDisconnect() is called to disconnect the service.
13.6 HSS Packetized Operation
13.6.1 Packetized Connect and Enable
ixHssAccPktPortConnect()
After the HSS component is configured, ixHssAccPktPortConnect() has to be called to connect the
client application with the packetized services. This function is responsible for connecting a client
to one of the four available packetized ports on a configured HSS port.
There are four packetized services per HSS port, so this function has to be called once per
packetized service.
Note: This functions structures have changed significantly in software release 2.0 and the function is no
longer directly compatible with previous versions.
The client uses this function to:
• Pass data structures to configure the HDLC coprocessor
• Register a Rx call back function for Rx data processing
• Register a callback function to request more Rx buffers
• Register a callback function to indicate Tx done
• Pass a flag to turn HDLC processing on or off
The HDLC configuration structure sets up:
• What to transmit when an HDLC port is idle
• HDLC data endianness
• CRC type to be used for this HDLC port.
The parameters for ixHssAccPktPortConnect() include:
• IxHssAccHssPort hssPortId — The HSS port ID. There are two identical ports (0-1).
• IxHssAccHdlcPort hdlcPortId — This is the number of the HDLC port and it corresponds to
the physical E1/T1 trunk (i.e., 0, 1, 2, 3).
• BOOL hdlcFraming — This value determines whether the service will use HDLC data or the
raw data type (i.e., no HDLC processing).
• IxHssAccHdlcMode hdlcMode — This structure contains 56Kbps, HDLC-mode configuration
parameters.
• BOOL hdlcBitInvert — This value determines whether bit inversion will occur between
HDLC and HSS coprocessors (i.e., post-HDLC processing for transmit and pre-HDLC
processing for receive, for the specified HDLC Termination Point).