Filter
Top Products
Intel
®
IXP400 Software
Codelets
Programmer’s Guide IXP400 Software Version 2.0 April 2005
Document Number: 252539, Revision: 007 311
— Configuring Port-1 to automatically transmit frames and Port-2 to receive frames. Frames
generated and transmitted in Port-1 are looped back into Port-2 by using cross-over cable.
— Configuring and performing a software loopback on each of the two Ethernet ports.
— Configuring both ports to act as a bridge so that frames received on one port are
retransmitted on the other.
• Ethernet management services:
— Adding and removing static/dynamic entries.
— Calling the maintenance interface (run as a separate background task)
— Calling the show routine to display the MAC address filtering tables.
IxEthAccCodelet demonstrates the use of many of the access-layer components.
23.8 HSS Access Codelet (IxHssAccCodelet)
IxHssAccCodelet tests packetized and channelized services, with the codelet acting as data source/
sink and HSS as loopback. The codelet will transmit data and will optionally verify that data
received is the same as that transmitted.
Codelet runs for a user selectable amount of time. This codelet provides a good example of
different Intel XScale core-to-NPE data transfer techniques, by using mbuf pools for packetized
services and circular buffers for channelized services.
23.9 Parity Error Notifier Codelet (IxParityENAccCodelet)
The IxParityENAccCodelet shows how to integrate parity error detection and error handling
routines into a client application, using IxParityENAcc. The API is based upon capabilities
available on the Intel
®
IXP46X product line processors. This codelet demonstrates the following:
• How to initialize IxParityENAcc.
• How to configure IxParityENAcc or modify IxParityENAcc configuration.
• How to register callback with IxParityENAcc.
• How to register data abort handler with kernel (only for VxWorks).
• How to inject ECC error.
• How to spawn a task to initiate SDRAM memory scan.
• How to scrub memory to correct single bit ECC error.
• How to handle various parity errors reported by IxParityENAcc.
• How to determine whether the data abort is due to multi bit ECC.
• Error initiated when Intel XScale core accesses SDRAM.