Intel IXP400 Frozen Dessert Maker User Manual


 
Intel
®
IXP400 Software
Access-Layer Components: UART-Access (IxUARTAcc) API
April 2005 IXP400 Software Version 2.0 Programmer’s Guide
294 Document Number: 252539, Revision: 007
UART IOCTL
Baud rate set/get
Parity
Number of stop bits
Character length 5, 6, 7, 8
Enable/disable hardware flow control for Clear to Send (CTS) and Request to Send (RTS)
signals
21.4 UART / OS Dependencies
The UART device driver is an API than can be used to transmit/receive data from either of the two
UART ports on the processor. However, it is expected that an RTOS will provide standard UART
services independent from the IxUartAcc device driver. That is, the RTOS UART services will
configure and utilize the UART registers and FIFOs directly.
Users of the IxUartAcc component should ensure that the use of this device driver does not conflict
with any UART services provided by the RTOS.
21.4.1 FIFO Versus Polled Mode
The UART supports both FIFO and polled mode operation. Polled mode is the simpler of the two
to implement, but is also the most processor-intensive since it relies on the Intel XScale
®
Core to
check for data.
The device’s Receive Buffer Register (RBR) must be polled at frequent intervals to ascertain if data
is available. This must be done frequently to avoid the possibility of buffer overrun. Similarly, it
checks the Transmit Buffer Register (TBR) for when it can send another character.
The FIFO on the processor’s UART is 64 bytes deep in both directions. The transmit FIFO is 8 bits
wide and the receive FIFO is 11 bits wide. The receive FIFO is wider to accommodate the
potentially largest data word (i.e., including optional stop bits and parity 8+2+1 = 11).
Interrupts can occur in one of two ways. One is when the FIFO has reached its programmed trigger
level (set by the FIFO Control Register [FCR]). The other is when a character timeout has occurred
(also set in the FCR). The driver will implement both modes of operation.
The default setup for the UART is:
9,600 bps baud rate
8-bit data word
One stop bit
No parity
No flow control
Interrupt mode (Polled for generic interface)