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IXP400 Software
Access-Layer Components: Parity Error Notifier (IxParityENAcc) API
Programmer’s Guide IXP400 Software Version 2.0 April 2005
Document Number: 252539, Revision: 007 235
16.2.2.2 Switching Coprocessor in NPE B (SWCP)
The Switching Coprocessor generates 8-bit parity – 1 bit per each byte of the 64 bit (8-byte) entries
in its SRAM. These parity bits will be generated and captured along with the 64 bits of data during
a write operation. The subsequent read operation will again generate parity bits from the 64 bits of
data and compare against the ones stored. If there is a mismatch, an interrupt is issued to the Intel
XScale core through the interrupt controller.
A parity error in this component would also generate an NPE-B interrupt as an external
coprocessor error.
16.2.2.3 AHB Queue Manager (AQM)
The AQM, on identifying a parity error from its internal memory, will return an ‘AHB Error’
response on the AHB bus to the requesting master. The interrupt context then refers to the address
of either a queue entry or queue configuration entry, whose access resulted in failure. For queue
entry address cases, the client application should treat the queue entry as invalid. The client should
respond to a queue configuration parity error by rendering the entire queue invalid.
16.2.2.4 DDR SDRAM Memory Controller Unit (MCU)
When the MCU detects a single-bit error, the word is corrected before it is delivered so that the
Intel XScale core gets a correct copy of the defective memory location contents (which still
contains the uncorrected value). For multiple-bit errors, no correction is possible and an error
response is placed on the bus visible to the Intel XScale core. In either case the interrupt context
refers to the address of the access that failed. The MCU keeps track of two such parity errors at any
point in time and notifies of an overflow if more than two parity errors occurred at the same time,
in which case the address will not be logged.
16.2.2.5 Expansion Bus Controller
The Expansion Bus Controller, upon receiving a parity error on the Expansion Bus, terminates the
transaction and responds on the South AHB bus with an “AHB Error” response for an outbound
read initiated by an internal master. It will respond similarly in situations where an inbound write is
initiated by an external master. It then provides an interrupt to the Intel XScale core with a context
containing a reference to the address of the access that contained the invalid data.
16.2.2.6 PCI Controller
The PCI Controller will send an interrupt to the Intel XScale core upon detecting a parity error in
the following scenarios:
• read and write data transfers from AHB devices to PCI
• write data transfer from PCI to AHB devices.
For a read transaction initiated from PCI onto AHB, the MCU would detect any parity errors and
send an interrupt to the Intel XScale core.