Intel IXP400 Frozen Dessert Maker User Manual


 
Intel
®
IXP400 Software
Endianness in Intel
®
IXP400 Software
April 2005 IXP400 Software Version 2.0 Programmer’s Guide
356 Document Number: 252539, Revision: 007
27.5.3.2 NPE Downloader — IxNpeDl
This component utilizes the NPEs’ Message Handler and Execution Control registers. All registers
are word-wide (32 bits). Such registers are best set up using Little-Endian Address Coherent mode.
However, this would cause the component to have differing behavior between some operating
systems. As a result, the decision was made to make the NPE Execution Control registers Data
Coherent.
All register reads/writes occur via the following functions, defined in npeDl/include/
IxNpeDlMacros_p.h
IX_NPEDL_REG_READ()
IX_NPEDL_REG_WRITE()
27.5.3.3 NPE Message Handler — IxNpeMh
This component is dependent upon NPE Message Handler and Execution Control registers. All
registers and hardware FIFOs are word-wide (32 bits).
Address Coherent Little-Endian mode is used for messages sent via the Message Handler interface.
For example, the ixNpeMhMessageSend function is defined as follows:
typedef struct
{
UINT32 data[2]; /*the actual data of the message */
} IxNpeMhMessage;
Although the registers would be ideally accessed in Address Coherent mode, a system-wide
decision to put IXP400 software peripherals in Data Coherent mode means the contents of the
“data” within the Message Handler is modified by the underlying access-layer software.
27.5.3.4 Ethernet Access Component — IxEthAcc
The decision to set up the SDRAM in Data Coherent Little-Endian mode is driven by the primary
assumption that there will be more payload than control data structures exchanged between the
NPEs and Intel XScale core.
This approach also lends itself to using Address Coherent mode for the control structures, and, if
required for a future OS porting, should be easily implemented in a particular operating system
environment. Some of the information detailed below is intended to facilitate use of Address
Coherent mode should it be desired. It is not intended to imply that Address Coherency is used in
this component in the current software from Intel.