Filter
Top Products
DATA
(instrument
bus
data)
query
l\
F--{
oaraz
}-.-
\ -
:^p0RjdglE*tF'
4416-08
Response
to DATA
query
a4t$09
Combined
ADDR
command
and DATA
command
Malntenance
-
494Alttg4Ap
Service
Vol. I
The address
command
may
precede
a
data com-
mand or
query
to
identify
the instrument
bus
location
as
part
of
the same
m€ssage.
Enors
related
to
these commands
are 41
,
invalid
DATA
or
ADDR
argument
contents,
and
42,
DATA
direction
not compatible
with
ADDR
direction.
Instrument
Bus
Registers
Registers
provide
the
link
between
the instrument
bus
and
microcomputer
controlled
functions.
The
regis-
ters are
defined here
in
the same
order
as
they
appear
in
the Diagrams
section.
The
definitions
are
provided
to
help
in
constructing
DATA
commands
and interpreting
responses
to DATA
queries.
The
data is
presented
here as
binary.
In
some
cases
a
data value occupies
the entire
register
width;
for
instance,
a
value
in
digital
storage.
tn other
cases,
a
single
bit or
group
of
bits in
the
register
forms a code;
for
instance,
the upper
five
bits in
the sweep
rate and
mode register
indicate
the sweep
timeldivision.
The
meaning
of the
data
is
not
fully
defined
here; ref€r
to
the d€scription
of
the
circuit
module
in
Section
5 for
details.
To
use
the
binary
codes
presented
here with
the
DATA
command
and
query
statements,
you
must
con-
vert_
binary to hexadecimal.
The
binary
code
number
01001011
i$ used
as
an
example
in
the
following
steps.
1.
Group
the lower
four
bits
and
th€
upper four
bits
(break
the data
byte in
half).
01001011
-
0100
1011
2.
Convert
each
group
of
four
bits
to
a
hexadecimal
digit. Hexadecimal
digits range from
0 to
F
in
the
sequenc€
01
23456789A8CDEF.
0100
-
4
1011
-
B
(i.e..
8+0+2+1-11,
which is
hexadecimat
B)
3.
Group the two hexadecimal
digits
together, keep-
ing
their
respective
places.
4 and
B
mak€
the two-digit
hexadecimal
number
48
The infornation
in Table
6-13
is
separated
by
regis-
ters.
The
following information
is related
to
the table
information
by leading
alpha
designators.
A. Variable
Resolutlon
(refer
to diagram 20)
The microcomputer
writes
to two
variable
resolution
registers.
The data MSB steers
the
other
bits that are
defined
into
the desired register.
When
DB7
equals
1, it
steers DBo
through
DB2
to
select
the
resolution
bandwidth. WhEn DB7
equals
0,
it
steers DB6
through
DBo
to
select
the amount of
gain
added in
the
VR s€c-
tion and
the band
leveling
gain
(gain
adjustment
related
to
front-end
response in each
band).
These two
func-
tions are addressed and
set
together
by the
same
data
byte.
B.
Log
and
Video
Amplifier
(refer
to diagram 23)
There
are
two
registers
that
receive
data from
the
microcomputer.
One
register controls
vid€o
offset (78)
and
the
other controls
the display modes and the verti-
cal
scale factor
(79).
C. Video
Processor
(reler
to diagram 24)
Register 7C controls out-of-band
clamping, video
fi
ltering,
and
leveling.
D. Digital
Storage,
Vertical
(refer
to diagram
25)
Registers 7A and FA on
the V€rtical Digital Storage
board transfer
display data to
and
from
the
microcom-
puter
for spectrum analyzer
GPIB operations.
Register
78 controls
digital
storage
functions.
E. Z-Axis
&
RF
Interface
(refer
to digram
28)
Register
4F on
the
Z-Axis
&
RF Interface board
enables
Z-axis
and
RF attenuator control. Register CF
reports
power
supply status.
F.
Crt
Readout
(refer
to diagram
30)
Register
5F
controls crt
readout and
data
steering.
Register 2F
accepts data
from
the
microcomputer.
o
o
O
o
I
o
o
o
o
o
o
I
o
t
o
a
o
C
o
t
a
o
(l
o
a
o
o
o
o
)
o
o
o
o
t
o
o
o
a
a
C
o
o
o
6-56