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Theory
of
Operation
-
4g4ful4g4Ap
Servlce,
Vot.
i
Table
7-3
BANDWIDTH
SELECTION
Bandwidth
DBO
DBl
DB2
3 MHz
t
MHz
100
kHz
10
kHz
1 kHz
100
Hz
10
Hz
1
1
0
1
0
1
0
00
11
10
10
0'l
01
11
Filters
are
selected
by diode switching.
Series and
shunt
diodes
are
at
the input
and
output
of
each filter,
The
instrument
allows
only
one
filter
to
be
selected
at
a
lF
SECTTON
(Diagram
S)
The
lF
section
receives
the
lO
MHz
lF
signal
from
the
3rd
converter,
establis_hes
the
system
resolution,
levels
the
gain
across
the
frequency
i"ng.,
logarithmi_
cally
arnplifies
the
signal,
and
Oetecis
the-signai
to
pro_
duce
the video
output
to
the
Display
"""itn.
-
System
bandwidth
resolution
is
selectable
from
3 MHz
to
10
Hz.
This
s.etection
is
pe;orm€d
by
the
Variable
Resotution
circuits
and
is
"6niiot"O
over
the
instrument
bus.
Generally,
two
sets
oi
Riters
ar€
used
to
establish
each
bandwidth.
A
uano-pasi
filter
is
also
included
at
the circuits
output.
Significant gain
is
al.s:
prgvided
by
severat
stages
of
amplification
within
the
Variable
Resoiution-circuit
block.
Other
gain
steps
are
also provided
by-switching
gain
blocks
in
or
out
of
tle^ signal
path.
ffiese
gain
blocks
provide
-10,
+10,
*20,
or
+dOdB
ot
aOOitionat
gain
when
switched
in
combination.
..Logarithmic
amplification
of
the signal
is
required
to
calibrate
the
graticule
in
dB/division.
-Tt
i.
i"
performed
!y
:.."y".n
stage
amptifier
t-hat
proOuces
Ln
output pro-
portional
to
the logarithm
of
the
input.
thus,
tne
screen
displacement
can
be
selectable
tor
ttre
amount
of
change
per
division,
and
can
Ue
projortional
to
the
input
level
.change.
For
exampl"i
irilt"
10dB/div
display
mode,
each
division
of
'displar"r.nt
on
the
screen
represents
a
signal
level
change
of
10
dB
regardress
of
whether
it
is
at
the
top
or
50ttom
of
the
screen.
The
detector
follows
the
logarithmic
amplifier
to
pro-
9t"9
"
positive-going
output
silnat
that
is
apptieO
to
the
display
section
as
the
V|DEO
signat.
Variabfe
Resolution
(Diagrams
19,
19,104;Id,'and
21)
The
Variabte
Resotution
(VR)
assembty
(A6g)
and
the
10
Hzl100
Hz
Bandpass
Firter
aiiJmOty
inOSy
establish
the resolution
bandwidth
and provide
ipproxi_
Ta.tely
41
dB
of
system
gain.
The
Vi
assembiy
con-
sists
of
two
sets
of
filters
plus
gain
stages.
The
1.0 Hl100
Hz
Bandpass
Fitter
issem-Oty
acts
as
part
of
the VR
circu.its,
but
is
physicaily
in a
seiarate
assembty.
Since
the input
to
the
VR
circuits
'is
nominalty
at
-35-dBm
and
the
Log
Amptifier
input
,"quir""
*6
dBm
for
full
screen,
the
VR
circuits
mi.,.t prduiOe
the
gain
difference.
The
VR suppties
30
dB
oi
aOJifionat
lain
and.
10dB
of
gain
reduction
for
alt
verticat
disptay
modes.
Physically,
the
VR
assembly
contains
two
sub-
assemblies
that connect
together
and
plug
onto
the
instrument
Mother
board.
The
input
"ir",lit-i
are
in
one
sub-assembly
and
the
output
circuits
and
digital
inter-
face
are
in
the
other.
Each
of
the
sub-assemblies
con-
sists
of
boards
that
plug
onto
a four_layer
VR
Mother
board
with
a
ground
plane
on
both
outside
layers.
Only
pow€r
supply
and
control
voltages
travel
through
th6
VR
Mother
board.
All signat
coniections
are
by
joaxial
cable.
VR
Input
(Diagram
19)
The
VR
Input
circuit
receives
the
_3S
dBm
I0
MHz
signal
from
the
Ard
Mixer
through
J6g3.
This
signal
goes
through
an
amplifier
and
an
attenuator.
The
signal
is
applied
to
broadband
feedback
amplifier
01029,
which
is
biased
for
a
large
output
current
(approximately
50
mA)
to
reduce
intermodula-
I_o-1 I:t:ni9n.
This
performance
is
provided
primarily
through
the large
current
capacity
by negative
feedbaci
through
resistor
R1025
and
by emittei
degeneration
resistor
R1023.
A
6 dB
attenuator
at
the
output
of
amplifier
elo2g
provides
a clean
50
ohm
output
to
the lst
Filter
Select
circuit.
1st
Filter
Setect (Diagram
t9)
The
1st
Filter
Select
circuit
operates
with
the
2nd
Filter
Select
circuit
through
banks
of switched
filters
to
set
the overall
system
bandwidth.
Data
bits
0,
1, and
2
from
the
data
bus
are
applied
to
decimal
decoder
lC
U4035 (it provides
a
low
signal
on
the appropriate
out-
put
pin
to enable
the selected
filter).
Bandwidth
setec-
tions
are
10
Hz
to 1
MHz in
decade steps,
and
3
MHz.
The
data
bits
select
a
bandwidth
filtei
according
to
Table
7€.
7-23