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Theory
of
Operatlon
-
4g4Al4S4Ap
Servlce,
Vol.
1
Table
7-4
GAIN
STEP
COMBINATIONS
Band
Leveting
Circuit (Diagram
20)
-
The
two amplifiers,
in
the
Variable
Resolution
Band
Leveling
circuit,
conect
gain
variations
through
the front
end.
These
band-to-band
variations
are
due
to the
different
modulation
products
out
of
the
lst
Converter
and
losses
through
the
preselector.
Nominal
signal
input
tevel
for
band
1
at
100
kHz
resolution,
in
the
Min
Distortion
mode,
is
_12
dBm.
This
decreases
sorne
for
the
higher
bands.
The
output
level
is
about
-2
dBm.
This
output
level
is
kept
con_
stant
by
using
the
microcomputer
to adjust
the
amplification
through
this
circuit
for
each
banct.
The
two amplifier
stages
on
this
board
are
similar
to
llre
10
dB
gain
steps
circuits.
A
stage
consists
of
a
three-transistor
circuit
using
a
diffeiential
pair
con-
nected
to an
emitter-follower.
The
gain
is controlled
by
altering
the
feedback
network.
.The
first
stage
(e2015,
e2019,
and
e1025)
has
a
gain
range
of
13.5
dB
by controiling
the
bias
of
ptN
diode
CR2021
in
the feedback
loop.
Bias
for
this
diode
depend-s
on-
a
voltage
divider
network
consisting
of
an
array
of
variabla
resistors
on
the VR
Mother
board
#2,
468A2,
with
the
divider
network
setected
by
the
micro-
computer.
.
Jh"
second.stage
(e1031,
e1o3g, and
e1041)
is
similar,.
except
the
gain
change
is
a
one
step
change
of
approximately
12.5
dB.
This
gain
step
occurs
in
the
higlrel
bands
(4
through
i1).
tf required,
gain
change
is
activated
by
the
microcomputer
through
user-selected
diodes and
transistor
e2046.
The
spectrum
analyzer
is
normally
calibrated
with
the
band 1
gain
control
resistor
set
for
rninimum
gain.
Gain is
then
added
as
required
for
the
higher
bands.
Data
bits
3 through
6 select
gain
for
each
-banO
selec-
tion.
The
output
from
this
board
is
applied
through
con_
nector
EE
to
the
2nd
Filter
Select
circuit.
VR
Mother
Boards
{Diagram
18)
The
circuits
on
the
VR
Mother
boards
provide
address
and
data
decoding,
band
leveling
control,
and
plwer
supply
and
control
signal
interfacing
to
the
other
VR
boards.
The
VR
Mother
board
#1
(A6SA|)
provides
decoupled
power
supplies
and
interface
lines
to
the VR
Input (A6849),
lst
Fitter
Setect
(A68A4),
10
dB
Gain
Steps
(A68A5),
and
20
dB
Gain
Steps
(A6gA6)
boards.
The VR
Mother
board #2
(A6gA2)
provides
address
and
data
decoding
and
gain
controf
for
the Band
Levef-
ing
circuit.
The VR
Mother
board
#2
provides
power
supply
voltages
and
control
lines
to
the VR
Mother
board
#1
(A68A1),
Band
Leveting (A68AZ),
2nd
Fitter
Select
(468A8),
and
the
VR
post
Amptifier
(A6gA9).
Address
and
data valid
lines
from
the instrument
address
bus are applied
to address
decoder
U4O2Z.
Data
bit
7 is
applied
to the
decoder,s
select
input A as
a supplemental
address
bit. This
bit
selects
either
an
address
to latch
data
for
th€ resolution
bandwidth
selection
or
an address
to
latch
data
for
gain
step
selection
and
band identification.
Data
latches
u3010 and
u3017
monitor
the data
bus
at
the sel€cted
address.
Latch
u3010
stores
the filtEr
s€lect
data
that controls
th€ lst and
2nd Filter
Select
circuits.
U3017
latches
the
gain
selection
and
band
identification
data. Latched
data
bits
0,
1,
and 2
(output
pins
2,
5, and
6) switch
transistors
e4095, e3035,
and
Q4037 to control
the
gain
switching
circuits
in
the 1O
dB
and 20
dB
Gain
Step circuits
through
VR Mother
board
#1.
The
output
on
pins
15, 16,
19,
and 12 ol
U3017
(corresponding
to data bits
3,
4,
5, and
6) are apptied
to
band decoder
U3023,
an
op€n collector
decoder. lf
band
1
is
selected,
pin
1 of
u3023
goes
low and if
band
2
is selected
pin
2
goes
low, etc.
This output in con-
junction
with a 7.5
V reference
source (provided
by
operational
amplifier
U30388
and
driver
transistor
03036)
produces
a
voltage at
the
output of a opera-
tional amplifier,
U3038A. This
voltage
is
indicative
of
the
gain
that
must
be
set for
each
band
so
the
level
remains
constant
at
the output
for all
bands.
Galn Required
Data
Biis
468A5
Pin
N
(10
dB)
468A6
2
1
0
Pin
V
(20
dB)
Pin
Y
(10
ru
ots
20
dB
30 dB
40
dB
0
1
1
1
0
0
0
1
1
0
1
1
0
1
0
0
1
0
0
0
1
1
1
0
7-27