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MELSOFT
8 ACCESSIBLE DEVICES AND RANGES
Access Target
Device
(Device Name)
A1N
A0J2H
A1S(-S1)
A1SH
A1SJ(H)
A2C(J)
A2N(-S1)
A2S(-S1)
A2SH(-S1)
A1FX
A2A(-S1)
A2U(-S1)
A2US(-S1)
A2AS
(-S1/-S30)
A2USH-S1
Q02(H)-A
Q06H-A
A3N
A3A
A3U
A4U
QnACPU
QCPU
(Q mode)
LCPU Q12DCCPU-V QSCPU
FXCPU
Motion
controller
CPU
(Z)
*1*2
Index register
(V)
*1*2
(R) *3
*4
File register
(ZR)
*3
Extended file register
(ER
\R)
Link input
(J
\X)
Link output
(J
\Y)
Link relay
(J
\B)
Link special relay
(J
\SB)
Link register
(J
\W)
Direct
link
Link special register
(J
\SW)
Special direct buffer memory
(U
\G)
*5
*1: Accessible to FX0NCPU, FX1SCPU, FX1N(C)CPU, FX2N(C)CPU, FX3GCPU, FX3U(C)CPU only when using the FX extended port.
*2: It is not possible to write to more than 2 points successively using WriteDeviceBlock or WriteDeviceBlock2. (Writing to only 1 point is
allowed.)
*3: Disabled for the use of Q00JCPU or Q00UJCPU.
*4: When accessing to FX series CPU other than FX
3GCPU and specify FX3U(C)CPU, specify the data register. The file register (R) can be
specified only when accessing to FX
3GCPU or FX3U(C)CPU.
*5: In a multi-CPU configuration, read from the shared memory of the host CPU cannot be performed.
In addition, write to the shared memory cannot be performed independently of the host or other CPU.