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MELSOFT
8 ACCESSIBLE DEVICES AND RANGES
8.13 For Q Series Bus Communication
This section provides the accessible devices and accessible ranges for Q series bus
communication.
8.13.1 Accessible devices
The following table indicates the accessible devices for Q series bus communication.
Access Target Access Target
Device
(Device Name)
Q02(H), Q06H,
Q12H, Q25H,
Q02PH, Q06PH,
Q12PH, Q25PH
Device
(Device Name)
Q02(H), Q06H,
Q12H, Q25H,
Q02PH, Q06PH,
Q12PH, Q25PH
Function input (FX)
Link special relay (SB)
Function output (FY)
Link special register (SW)
Function register (FD)
Step relay (S)
Special relay (SM)
Direct input (DX)
Special register (SD)
Direct output (DY)
Input relay (X)
Accumulator (A)
Output relay (Y)
(Z)
Internal relay (M)
Index register
(V)
Latch relay (L)
(R)
Annunciator (F)
File register
(ZR)
Edge relay (V)
Extended file register (ER \R)
Link relay (B)
Link input (J \X)
Data register (D)
Link output (J \Y)
Link register (W)
Link relay (J \B)
Contact (TS)
Link special relay (J \SB)
Coil (TC)
Link register (J \W)
Timer
(T)
Present value (TN)
Direct
link
Link special register (J \SW)
Contact (CS)
Special direct buffer memory (U \G)
*
1
Coil (CC)
Counter
(C)
Present value (CN)
Contact (SS)
Coil (SC)
Retentive timer
(ST)
Present value (SN)
*
1: In a multi-CPU configuration, read from the shared memory of the host CPU cannot be performed.
In addition, write to the shared memory cannot be performed independently of the host or other CPU.