Filter
Top Products
Peak/Pit
Detection
Refer to function block J of the Al6 fast ADC assembly schematic diagram in the
HP 8560 E-Series Spectrum Analyzer Component Level Information.
Peak detection or pit (negative peak) detection can be enabled whenever the sample rate is
less than 12 MHz (sweep times greater than 50
ps).
Peak detection uses the maximum value
of all the samples taken within each bucket (between adjacent display points). Pit detection
uses the minimum value of all the samples taken within each bucket. And sample detection
uses the last sample of all the samples taken within each bucket.
The different detection modes are implemented by selectively clocking latch U30, depending
on the state of
LP/Q
which is generated in PAL
Ul
(block A). When
LP/Q
is low,
U30
is clocked by WCLK. When
LP/Q
is high,
U30
is not clocked.
LP/Q
is a function of the
12M-SEL,
SCLK-1, LSAMPLE, LPEAK, P-LO, and P-HI signals. See Table 8-12.
If the sample rate is 12 MHz,
12M-SEL
is high, which forces
LP/Q
low so that every sample
is clocked into latch
U30
and latched into RAM U32 (block K). If the sample rate is less than
12 MHz and the detection mode is peak or pit, the SCLK-1, LPEAK, P-LO, and P-HI signals
control the
LP/Q
signal. In these detection modes, latch
U30
stores the peak or pit value of
the samples taken for each bucket. The 8-bit digital magnitude comparator, U31, compares
the input byte (P) with the output byte (Q) from latch U30. When P is greater than Q,
P-LO is low (0)
and P-HI is high (1). When P is less than Q, P-LO is high (1) and P-HI is
low (0). When P is equal to Q, P-LO and P-HI are both low (0). See Table 8-12.
Table 8-12.
LP/Q
Truth Table
I
Mode
I
LP/&
I
12M-SEL
I SCLK-1
I
LSAMPLE
I
LPEAK
I
P-LO
I
P-HI
I
12MHz
L
H
X
X
X
x x
SAMPLE L
X
X
L
X
x x
POS
PEAK
NEG
PEAK
(Pit)
Clocking
Peak/Pit
Sample
L
H
H
H
-I
L
H
L
L
L
L
L
H
L
L
H
c
L
L
X
32
K-Byte
Static
RAM
Refer to function block K of the Al6 fast ADC assembly schematic diagram in the
HP 8560 E-Series Spectrum Analyzer Component Level Information.
The static RAM stores the flash ADC samples that are taken when the fast ADC circuitry is
in the “write” mode. When not in the “write” mode, the static RAM is read by the CPU on
the A2 controller assembly to retrieve the fast ADC data.
The 8-bit Q bus connects the outputs of latch
U30
to the data port of static RAM U32.
ADC/lnterface
Section 8-33