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Theory of Operation
3-46
2715 Spectrum Analyzer Service Manual
TEXT3. This bit, when high, places page three of the four possible readout pages
on the CRT. Any number of text pages may be displayed on the CRT, however
the resulting display may not be readable, and will flicker severely.
TEXT2. This bit, when high, places page two of the four possible readout pages
on the CRT. Any number of text pages may be displayed on the CRT, however
the resulting display may not be readable, and will flicker severely.
TEXT1. This bit, when high, places page one (readouts) of the four possible
readout pages on the CRT. Any number of text pages may be displayed on the
CRT, however the resulting display may not be readable, and will flicker
severely.
DISPD. This bit, when high, enables the display of Waveform D on the CRT.
DISPC. This bit, when high, enables the display of Waveform C on the CRT.
DISPB. This bit, when high, enables the display of Waveform B on the CRT.
DISPA. This bit, when high, enables the display of Waveform A on the CRT.
Scroll Register. The Scroll Register is located at I/O memory location 0x0FA03.
The Scroll Register is write only register. R eading from this register will return
the vertical data currently stored in the Maximum Storage register. This value
may be either a maximum peak, if the acquisition mode is Max Peak, or sample,
if the acquisition mode is Sample. After reading this register, it is cleared.
Table 3- 10: Scroll Register
Bit
Number
Mnemonic
Activity
Level
Description
7 MCREG2 High Enables Mode Control Register 2
6 Not used —
5 Not used —
4 Not used —
3 SCRL3 High Readout Scroll bit 3
2 SCRL2 High Readout Scroll bit 3
1 SCRL1 High Readout Scroll bit 3
0 SCRL0 High Readout Scroll bit 3
MCREG2. This bit, when low, holds Mode Control Register 2 in the cleared
(disabled) state. Setting the MCREG2 bit high will allow successful writes to
Mode Control Register 2.
SCRL[0..3]. These four bits determine how far up the screen the bottom row of
text should be displayed, anywhere from 0 to 15 lines.