Filter
Top Products
Theory of Operation
2715 Spectrum Analyzer Service Manual
3-79
The tuning voltage path from the DAC to its varactor includes a temperature
correction from sensor (U9).
The 45.7 MHz signal from the SAW filter is presented to the MC44301
demodulator (U16). This device passes the signal through an AGC controlled IF
amplifier, then to a synchronous detector. The reference signal for the detector
comes from an internal PLL. Note that the oscillator for the PLL actually runs at
half frequency, and its output is frequency doubled on-- chip for use by both the
PLL’s phase detector and the synchronous video detector. This reduces stray
coupling between the oscillator’s external resonator (C41, C42, and L11) and the
IF input to the chip. The AFC error signal is a current from pin 5, and the video
output is a voltage (offset several volts positive) at pin 2. The video output is
passed through a single pole RC lowpass filter to strip off most of the color burst
signal, then through an emitter follower (Q10) on to the sync separator (U15).
The emitter follower is used because the input pin of the sync separator uses an
active diode clamp DC restorer which prefers being driven from a low imped-
ance source. The lowpass filter also includes a video attenuator to properly
match the video amplitude to the sync slice level of the sync separator. A video
test pad is provided at the output terminal of the demodulator IC.
The control line SEC AM_EN is provided to reconfigure the demodulator for
positive modulated signals. When SECAM_EN is taken high, two actions occur.
First, Q9 turns on, which changes the operating mode of the demodulator IC.
Secondly, part of U8 selects AGC sense gate timing control from the back porch
output of the sync separator because the sync tip is not a viable place to sample
the video for AGC with positive modulation.
This section uses an LM1881 IC (U15) to produce composite sync, vertical sync,
and Even/Odd field flag signals (all at 5 V logic levels) from the demodulated
video. A non--retriggerable one--shot multivibrator (U12) in the horizontal sync
path serves to strip out the unwanted equalizing pulses during the vertical retrace
interval so that the resulting horizontal sync signal is a simple periodic pulse
train at the horizontal rate. This one--shot is set up for a time interval of about
3/4 of the horizontal sweep period, and the feedback path from the “Q” output to
the “A” input serves to block triggering until timeout occurs, thus preventing
triggering by the equalizing pulses. If this process starts up out of sync, correct
sync is automatically re--established within one scan line of when the equalizing
pulses end. The horizontal sync, vertical sync, and Even/Odd flag signals are
buffered by U2 and sent to the Digital Options board as H_SYNC, V_SYNC,
and E/O_L respectively to drive the instrument’s gate timing circuits.
Video Detector
Sync Separator