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Theory of Operation
2715 Spectrum Analyzer Service Manual
3-67
The reference/period counter consists of devices U295, U380, and counter one of
U470. The reference counter is fed from the 100 MHz Reference Oscillator.
The IF counter consists of devices U370 and counter two of U470. The IF
counter is fed from the IF input and ranges in frequency from 5 MHz to 15 MHz.
The Frequency Counter Control Register (U385) contains all of the signals
necessary to run and control the Frequency Counters. The following are
descriptions for each of the signals:
H The TMRGATE signal (bit zero) is used to enable all of the counters in
U470. This signal is active (1) when counting is being performed.
H The CTR100MH signal is used to enable the 100 MHz buffer amplifier in
the Frequency Counter Buffer Amplifier section.
H The CLOAD-- signal is used to load counters U370, U380, and U480, with
the data present at the data inputs. This allows the counters to be set to any
starting point.
H The RESET signal is used to set the counting flip flops (U195) to a known
value.
H The VID_EN, IF_EN, CF C_EN, and OPT_EN enable the detect video, IF,
CFC, and optional input buffer amplifiers, respectively.
The Buffer Amplifier section consists of an ECL differential line receiver for
each input. The noninverting input of each receiver is connected to the signal
input, while the inverting input is connected to a control signal. The control
signals from the Frequency Counter Control Register are fed into pnp transistors
that act as saturated switches. These switches are then used to enable or disable
the associated receiver. Immediately following the first receiver is a second
receiver to help buffer the signal. The output of the second receiver is fed into a
level shifting transistor that sets the output TTL levels.
On the 100 MHz input, prior to ECL to TTL translation, an ECL flip flop (U195)
is used to synchronize and divide the signal frequency by two.