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2715 Spectrum Analyzer Service Manual
Figure 3-17: Timing Diagram for a Typical Write to the Control
Register 3-50...............................................
Figure 3-18: Timing Diagram of a Typical Sweep for the Horizontal
Track ing A/D Converter 3-51.................................
Figure 3-19: Sequence of Events When Writing Data to the
Waveform Memory 3-54.....................................
Figure 3-20: How a Vertical Scan is Performed 3-56.................
Figure 3-21: The Display of a Single Vector of a Waveform 3-57.......
Figure 3-22: A Single Column of Character Dots 3-57................
Figure 3-23: Vertical Output Integrator 3-58.......................
Figure 3-24: Microprocessor Block Diagram 3-61...................
Figure 3-25: Microprocessor Counter System (CPU) 3-62.............
Figure 3-26: Front Panel Block Diagram 3-83......................
Figure 3-27: How the Debounce Circuit Reacts to Key Closure 3-85....
Figure 3-28: Power Supply Primary Block Diagram 3-88.............
Figure 3-29: Display Amplifiers Block Diagram 3-91................
Figure 4-1: 3rd Order IM Test Setup (25 MHz Separation) 4-17.......
Figure 4-2: Harmonic Distortion Test Equipment Setup 4-18..........
Figure 4-3: 1 dB Compression Point Test Setup 4-20.................
Figure 4-4: Accessory Connector (J103) 4-22.......................
Figure 4-5: Test Equipment Setup for Checking Return Loss 4-28.....
Figure 4-6: Test Signal on Video Line 17 4-32.......................
Figure 4-7: Video Gating Check Waveform (NTSC Illustrated) 4-34....
Figure 4-8: IF Gating Check Waveform (NTSC Illu strated) 4-35......
Figure 5-1: Instrument Bottom View 5-5..........................
Figure 5-2: Display Storage Board Adjustment Locations 5-13........
Figure 5-3: Properly Adjusted Checkerboard Pattern 5-14...........
Figure 5-4: Locked 2nd LO and 5 MHz Bandpass Filter
Adjustments 5-16...........................................
Figure 5-5: Phase L ock CFC Module Adjustment and Test Point
Locations 5-17.............................................
Figure 5-6: Log Board Adjustmen t an d Test Point Locations 5-21.....
Figure 5-7: CAL Level Adjustment on Reference Oscillator Board 5-26.
Figure 5-8: RF Option Adjustment Locations 5-28..................
Figure 5-9: Variable Resolution Module Adjustment Locations 5-29....
Figure 5-10: Flatness adjustment test setup (all instruments
except Op tion 50) 5-34.......................................