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Theory
of
Operation
-
494A/4g4Ap
Service,
Vol.
.l
Marker
lC.
Marker
lC
U9020
performs
several
func_
tions
on
the Horizontal
Digital
Storage
board:
In conjunction
with
Horizontal
Digitat
storage
tc
U5020, it cr€ates
the
two waveform
markers
and
the
update marker.
Controls the
processor
addresses
assigned
to
digi-
taf
storage
-7A,78,
FA,
and FB.
Creates
the fast-retrace
blanking
pulse
DSBLANK.
Takes control
of
the address
lines
to
the display
RAM when
the
microprocessor
accesses
the digit;l
storage
data.
To create
the
waveform
marker,
it
monitors
the hor_
izontal
display
bits, HD0-9,
and
the
CURS and
B-A
sig-
nals. When
these
lines
indicate
the
display has
reached
a
point
that matches
on
of
hffo
points
previously
stored
in
the lC
by the
microprocessor,
the lC
sets
A INTEN_
SITY high, causing
U5020
to repeatedly
disptay
the
same
point
until
A INTENStry goes
low again
(which
it
does
after
a number
of
DS
ENBL
cycles
previously
stored
in
the lC
by
the
microprocessor).
The
update
marker
is
initiated
by a
comparator
detecting
that
the analog
sweep
and
the disptay
sweep
have crossed
as
explained
elsewhere.
U3O2O
detecti
this
event
on
the CSLFS
line.
lf the
VALID tine
is
high
when
this
occurs,
U3020 sets
INTENSITy
high,
causlng
U5020
to
repeatedly
disptay
the same
point
untit 15
DS
ENBL
cycles
have
passed,
Then
INTENS|TY
goes
tow
again.
U3020
monitors
HD9
to
generate
the DS
BLANK
pulse.
When
HD9
goes
from high
to low and
the
CUR-
SOR
line is low,
U3020 sets
DS
BLANK
high
for one
DS
ENABLE
cycle.
When
the microprocessor
wants
to
read
valu€s
from
or
write
data
to
the waveform
memory,
it first
sends
a
starting
address
to
u3020.
circuitry on
the vertical
Digital
storage
board
(A61A1)
controts
the
BUs
GRANT
line which
indicates
when
U3020
can actually
access
the
digital
storage
RAM
without
disturbing
the disptay.
When
BUS
GRANT
goes
tow,
U9020
(instead
of
U5020)
drives
HD0-9.
The Vertical
Digital
Storage
board also
generates
an
INCR
ADRS
(lncrement
Address)
pulse
for
each BUS
GRANT cycle.
U3020 increments
the
address
that
it
witl
assert
on
HD0-9
by
one
for each
INCR
ADRS
pulse.
The
microprocessor
loads
an initial
address
and
the
address register
outputs
are
applied
to tri-state
buffers.
Then,
the 10
bits of
address
from
the
counters
are
butfered.
Those
signals
are
multiplexed
onto
the HD
(horizontal
display)
lines
and
R/W
(read/write)
line
to the
memories.
These
buffers are
enabled
only
during
the
bus
grant
portion
of
the cycle
for
display
of
memory
7-46
data. At
all
other
times, horizontal control circuit
U5020
outputs
control the HD lines
to
det€rmine
the memory
address
for
update
of memory
data.
U3020 controls
and subdivides
the
addresses
assigned
to digital
storage. The Vgrtical
Digital
Storage
board
responds
to
addresses 7A,78,
and FA.
The Hor-
izontal
Digital
Storage
board
responds
to
addresses
7A,
78,
FA, and
FB.
The DV
(Data
Valid)
line
(which
ctocks
data to or frorn th€
microprocessor
from
th€ instrument
data bus)
goes
to U3020, which sends
a controlled
ver-
sion
of
this line,
VDV,
to the Vertical
Digital
Storage
board. When
the
addresses
on
the
Vertical
Digital
Storage board are
to be
addressed,
this
line
is active
and
none of
the
addresses on
the Horizontal
Digital
Storage
board
are
affected.
When
the addresses
on
the
Horizontal board
are
to be
accessed.
VDV ls held
low
by
U3020 regardless
of
DV.
Address 7A
on
the Horizontal
board is further subdi-
vided
into 7A.0
through
74.7
by
three bits
of
78 on
the
Horizontal
Digital Storage board. Access
to these
addresses
is
passed
between the two
boards by
U3020.
Reading from address
FB will
give
access
to the Hor-
izontal
board
regardless of
which
previously
had
acc€ss.
Sending
the bits to
78
on the Horizontal
board
to access
7A.6
(DB6-4-
110) will
pass
access
to the
Vertical
board. Sending
D86,5-11
to 7A.5 of
the
Hor-
izontal
board
will
also
pass
accesE
to the
V€rtical
board. Sending
DB6,5-10
to
7A.5 of
the
Horizontal
board
will
pass
access to the Vertical board,
but
only
for one
DV cycle.
Tracking
Digital-to-Analog
Converter. The 10-bit
digital-to-analog
converter operates as
part
of
the
loop
that
acquires a
binary
equivalent of
th€ swP
(sweep)
input
signal from the Sweep
board. Gonverter U4040
accepts
the
output from
the
10-bit
up/down
counter of
U5020
and converts that
output
to
an analog current.
The analog current is then subtracted
from
the SWP
signal
(which
is
applied at edge connector
pin
60
through
buffer U40298).
The result of
this
subtraction is
supplied
to
up
and
down
comparators in
U3050.
This
creates
the UP
or
DOWN signal,
as
appropriate,
to
con-
trol the
count
direction
of
the
1o-bit
up/down
counter
in
U5020.
The counter then counts
in
the
appropriate
direction, which changes
the
digital-to-analog
converter
output
to
reflect
the
proper
value.
Update
Marker Circults. These
circuits
create a
cur-
sor
to
show
the
present
update
location while a digital
storage
display refreshes.
The cursor is made by
stop-
ping
the
sweep for
a short
period,
allowing the
crt
phos-
phors
to brighten
at
that
spot. This occurs
at each
of
o
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