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10 SA-1110 Developer’s Manual
11.8.8 UDC Endpoint 1 Control/Status Register (UDCCS1) ...................................................286
11.8.8.1 Receive FIFO Service (RFS) .........................................................................287
11.8.8.2 Receive Packet Complete (RPC)...................................................................287
11.8.8.3 Receive Packet Error (RPE) ..........................................................................288
11.8.8.4 Sent Stall (SST) .............................................................................................288
11.8.8.5 Force Stall (FST)............................................................................................288
11.8.8.6 Receive FIFO Not Empty (RNE)....................................................................288
11.8.9 UDC Endpoint 2 Control/Status Register (UDCCS2) ...................................................288
11.8.9.1 Transmit FIFO Service (TFS).........................................................................289
11.8.9.2 Transmit Packet Complete (TPC)..................................................................289
11.8.9.3 Transmit Packet Error (TPE)..........................................................................289
11.8.9.4 Transmit Underrun (TUR) ..............................................................................290
11.8.9.5 Sent STALL (SST) .........................................................................................290
11.8.9.6 Force STALL (FST)........................................................................................290
11.8.10 UDC Endpoint 0 Data Register (UDCD0).....................................................................290
11.8.11 UDC Endpoint 0 Write Count Register (UDCWC)........................................................291
11.8.12 UDC Data Register (UDCDR) ......................................................................................292
11.8.13 UDC Status/Interrupt Register (UDCSR) .....................................................................292
11.8.13.1Endpoint 0 Interrupt Request (EIR) ...............................................................293
11.8.13.2Receive Interrupt Request (RIR) ...................................................................294
11.8.13.3Transmit Interrupt Request (TIR) ..................................................................294
11.8.13.4Suspend Interrupt Request (SUSIR).............................................................294
11.8.13.5Resume Interrupt Request (RESIR)..............................................................294
11.8.13.6 Reset Interrupt Request (RSTIR).................................................................294
11.8.14 SA-1110 UDC Register Locations................................................................................ 294
11.9Serial Port 1 – GPCLK/UART ...................................................................................................295
11.9.1 GPCLK Operation ........................................................................................................295
11.9.1.1 Simultaneous Use of the UART and GPCLK.................................................296
11.9.2 GPCLK Control Register 0 ...........................................................................................296
11.9.2.1 GPCLK/UART Select (SUS) ..........................................................................296
11.9.2.2 Sample Clock Enable (SCE)..........................................................................296
11.9.2.3 Sample Clock Direction (SCD).......................................................................296
11.9.3 GPCLK Control Register 1 ...........................................................................................297
11.9.3.1 Transmit Enable (TXE) ..................................................................................297
11.9.4 GPCLK Control Registers 2 and 3 ...............................................................................298
11.9.4.1 Baud Rate Divisor (BRD)...............................................................................298
11.9.5 UART Register Locations............................................................................................. 299
11.9.6 GPCLK Register Locations ..........................................................................................300
11.10 Serial Port 2 – Infrared Communications Port (ICP) ..............................................................300
11.10.1 Low-Speed ICP Operation ...........................................................................................301
11.10.1.1HP-SIR Modulation........................................................................................301
11.10.1.2UART Frame Format.....................................................................................302
11.10.2 High-Speed ICP Operation...........................................................................................302
11.10.2.14PPM Modulation..........................................................................................302
11.10.2.2HSSP Frame Format.....................................................................................303
11.10.2.3Address Field ................................................................................................304
11.10.2.4Control Field..................................................................................................304