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6 SA-1110 Developer’s Manual
9.5.3.1 CPU Preparation for Sleep Mode ..................................................................101
9.5.3.2 Events Causing Entry into Sleep Mode .........................................................101
9.5.3.3 The Sleep Shutdown Sequence ....................................................................101
9.5.3.4 During Sleep Mode ........................................................................................102
9.5.3.5 The Sleep Wake-Up Sequence .....................................................................103
9.5.3.6 Booting After Sleep Mode..............................................................................103
9.5.3.7 Reviving the DRAMs from Self-Refresh Mode...............................................104
9.5.4 Notes on Power Supply Sequencing............................................................................104
9.5.5 Assumed Behavior of an Intel® StrongARM SA-1110 System in Sleep Mode ............104
9.5.6 Pin Operation in Sleep Mode ....................................................................................... 106
9.5.7 Power Manager Registers............................................................................................107
9.5.7.1 Power Manager Control Register (PMCR).....................................................107
9.5.7.2 Power Manager General Configuration Register (PCFR)..............................108
9.5.7.3 Power Manager PLL Configuration Register (PPCR)....................................110
9.5.7.4 Power Manager Wake-Up Enable Register (PWER).....................................110
9.5.7.5 Power Manager Sleep Status Register (PSSR).............................................111
9.5.7.6 Power Manager Scratch Pad Register (PSPR) .............................................113
9.5.7.7 Power Manager GPIO Sleep State Register (PGSR)....................................113
9.5.7.8 Power Manager Oscillator Status Register (POSR) ......................................114
9.5.8 Power Manager Register Locations .............................................................................114
9.6 Reset Controller........................................................................................................................115
9.6.1 Reset Controller Registers ...........................................................................................115
9.6.1.1 Reset Controller Software Reset Register (RSRR) .......................................115
9.6.1.2 Reset Controller Status Register (RCSR)......................................................116
9.6.2 Reset Controller Register Locations.............................................................................117
10 Memory and PC-Card Control Module
10.1Overview of Operation ..............................................................................................................120
10.1.1 Types of Memory Accesses .........................................................................................122
10.1.2 Reads...........................................................................................................................122
10.1.3 Writes ...........................................................................................................................123
10.1.4 Transaction Summary .................................................................................................. 123
10.1.5 Read-Lock-Write ..........................................................................................................123
10.1.6 Aborts and Nonexistent Memory ..................................................................................124
10.2Memory Interface Reset and Initialization.................................................................................124
10.2.1 Hardware or Sleep Reset Procedures..........................................................................125
10.2.2 Software or Watchdog Reset Procedures ....................................................................126
10.3Memory Configuration Registers ..............................................................................................127
10.3.1 DRAM Configuration Register (MDCNFG)...................................................................128
10.3.2 DRAM Refresh Control Register (MDREFR) ...............................................................132
10.3.3 CAS Waveform Rotate Registers (MDCAS00, MDCAS01, MDCAS02,
MDCAS20, MDCAS21, MDCAS22) .............................................................................136
10.3.3.1 MDCAS Registers with Asynchronous DRAM...............................................136
10.3.3.2 MDCAS Registers with SDRAM and SMROM...............................................137
10.3.4 Static Memory Control Registers (MSC2 – 0) ..............................................................139
10.3.5 Expansion Memory (PC-Card) Configuration Register (MECR) ..................................142
10.4SMROM Configuration Register (SMCNFG) ............................................................................144
10.4.1 Changing SMROM RAS Latency .................................................................................147
10.5Dynamic Interface Operation ....................................................................................................148