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126 SA-1110 Developer’s Manual
Memory and PC-Card Control Module
through the "CBR" state and back to "idle". On the first pass, the "PALL" state is incurred
prior to the "CBR" state. See Figure 10-5.
7. In systems containing DRAM or SDRAM, enable banks by setting MDCNFG:DE[3:0]. For
each SDRAM bank pair that has one or both banks enabled, this will force a pass through the
"MRS" (mode register set) state and back to "idle". The MRS commands will program
SDRAM device(s) with the CAS latencies indicated by MDCNFG:TDL2x and
MDCNFG:TDL0x. The burst type and length will always be programmed to sequential and
one (1), respectively.
8. In systems containing SDRAM or SMROM, optionally enable auto-power-down by setting
MDREFR:EAPD and MDREFR:KAPD.
10.2.2 Software or Watchdog Reset Procedures
Software is responsible for controlling the following procedures when coming out of software or
watchdog reset. They must be completed prior to any SDRAM accesses or writes to MDCNFG or
MDREFR, to ensure that every SDRAM row is precharged prior to receiving the next bank activate
(ACT) or mode register set (MRS) command.
1. Disable all SDRAM banks by clearing MDCNFG:DE[3:0], without changing
MDCNFG:DTIM2 and MDCNFG:DTIM0.
2. Trigger a precharge all (PALL) command to SDRAM by attempting a nonburst read or write
access to any disabled DRAM bank.
3. Re-enable SDRAM banks by setting MDCNFG:DE[3:0].