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160 SA-1110 Developer’s Manual
Memory and PC-Card Control Module
10.5.6 DRAM/SDRAM Refresh
The SA-1110 provides support for CAS before RAS (CBR) refresh. When the DRAM interface is
enabled (by setting any of MDCNFG:DE[3:0] and setting MDREFR:DRI greater than zero), the
refresh counter starts counting up every memory cycle (2 CPU cycles) from 0. When its value
reaches the value in MDREFR:DRI times 32, the memory controller is notified that a refresh cycle
is due, the counter is cleared and resumes counting. After the current transaction completes, a
refresh cycle is performed. All four nCAS/DQM lines are driven low. Two memory clock cycles
later (4 CPU cycles), the four nRAS/nSDCS signals driven low. After MDREFR:TRASR+1
memory clock cycles, all nRAS/nSDCS and nCAS/DQM signals driven high and
MDCNFG:TRP0,2 is used to hold off subsequent DRAM accesses to allow for row precharge time.
Hardware or sleep reset clears the refresh counter. Software and watchdog reset do not affect it.
SDRAM CBR is performed simultaneously (and at the same interval) with the asynchronous
DRAM CBR refresh. The nSDRAS and nSDCAS signals are driven high in every cycle except the
first one: in which all of the enabled nRAS/nSDCS are driven low. This is done to ensure that the
SDRAM devices only receive NOP commands while nCAS/DQM and nRAS/nSDCS are being
held low for asynchronous DRAM refresh. If the SA-1110 detects that this is its first refresh cycle
after reset, a precharge all banks (PALL) command is executed prior to the auto-refresh (CBR)
command.
A single (non-burst) read or write to any disabled DRAM bank causes one refresh cycle to all
banks. Refresh cycles continue to occur while the CPU is in idle mode.
Figure 10-9 shows a timing diagram of a CBR refresh cycle.