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SA-1110 Developer’s Manual 105
System Control Module
The major concern is for power dissipation in sleep and requirements for the power supplies on the
processor during sleep. The SA-1110 generates these supplies using several on-chip regulators with
limited current capacity. Excessive activity on-chip pins might load these regulators beyond their
capacity and result in droop of the on-chip supplies.
One example is that of a component tied to one of the GPIO pins that constantly transmits to the
processor. If the system design indicated that activity from this detector should not bring the
SA-1110 out of sleep, the transitions from this GPIO might result in switching in the processor that
would exceed the sleep current limit.
This concern exists regardless of whether the GPIO is enabled as a wake-up source. Figure 9-3
shows the three power-related modes of the SA-1110 and the actions that cause transitions between
the modes.
Table 9-2 summarizes what power and clock supplies are used by each module within the SA-1110,
as well as the status of the power and clock supplies to each unit during each of the three
power-related modes.
Figure 9-3. Transitions Between Modes of Operation
IDLE
RUN
SLEEP
Power on, nRESET asserted
nRESET
negated
Force sleep bit set, or VDD or
battery fault pins asserted
Wait for interrupt
instruction
Wait for wake-up
event
System or
peripheral unit
interrupt
CPU clock held low; all
other resources active, wait
for interrupt
GPIO or RTC
alarm interrupt
VDD or battery fault
pins asserted
nRESET asserted
nRESET asserted
HARDWARE RESET
nRESET
asserted