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SA-1110 Developer’s Manual 287
Peripheral Control Module
Note: Due to the internal synchronization required by the SA-1110 UDC configuration registers, it is
possible for the CPU to write to the SA-1110 UDC registers and FIFOs too fast. So, a single write
to the SA-1110 UDC must be completed before another write may take place. To ensure that a
single write is completed, it is necessary to observe the effect of the write before another write may
take place. This can be accomplished by writing to a SA-1110 UDC register and then reading back
the same register two times. The second read-back should produce correct data.
11.8.8.1 Receive FIFO Service (RFS)
The RFS bit will be automatically set to 1 if the Receive Data FIFO contains 12 or more bytes (out
of 20). Because the FIFO is asynchronous, the exact threshold cannot be determined, but it is
guaranteed to be in this range. RFS = 1 is used to request DMA service for the FIFO.
11.8.8.2 Receive Packet Complete (RPC)
The RPC bit is automatically set to 1 after an OUT Packet has been received. When the RPC bit is
set, the RIR bit in the UDC Status/Interrupt Register will be automatically set to 1 if receive
interrupts are enabled. The RPC bit can be used to validate the other status/error bits in UDCCS1.
The RPC bit is cleared to 0 by the CPU writing a 1 to it. While the RPC bit is set, the SA-1110
UDC will issue NAK Handshakes to all OUT Tokens.
0h 8000 0014 UDCCS1 Read/Write
7 6 5 4 3 2 1 0
Reserved RNE FST SST RPE RPC
RFS
Reset
0 0 0 0 0 0 0 0
Bits Name Description
0RFS
Receive FIFO service (read-only).
0 – Receive FIFO has less than 12 bytes.
1 – Receive FIFO has 12 bytes or more.
1RPC
Receive packet complete (read/write 1 to clear).
0 – Error/status bits invalid.
1 – Receive packet has been received and error/status bits are valid.
2RPE
Receive packet error (read-only).
0 – Receive packet has no errors.
1 – Receive packet has errors; valid only when RPC is set.
3SST
Sent stall (read/write 1 to clear).
1 – STALL handshake was sent; valid only when RPC is set.
4FST
Force stall (read/write).
1 – Issue STALL handshakes to OUT tokens.
5 RNE
Receive FIFO not empty (read-only).
0 – Receive FIFO empty.
1 – Receive FIFO not empty.
7..6 —
Reserved.
Always reads zero.