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258 SA-1110 Developer’s Manual
Peripheral Control Module
Figure 11-13. Active Mode Pixel Clock and Data Pin Timing
A9003-01
L_FCLK
(VSYNC)
L_BIAS
(OE)
L_LCLK
(HSYNC)
L_PCLK
LDD[7:0],
GPIO[9:2]
Notes:
PCP - Pixel clock polarity:
0 - Pixels driven from data pins on rising edge of pixel clock.
1 - Pixels driven from data pins on falling edge of pixel clock.
Pixel 0 Pixel 2 Pixel 3Pixel 1
Data Pins Change
L_PCLK
Data Pins Sampled
by the Display
(PCP = 0)
(PCP = 1)