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214 SA-1110 Developer’s Manual
Peripheral Control Module
The RUN bit is the channel enable. The RUN bit is written to a 1 by the user when the channel is
ready for a transfer. The RUN bit can also be used to pause the channel in the middle of a transfer
by clearing it; when the RUN bit is set to a 1 again, the channel will resume from the current
pointer value using the current active buffer. If the RUN bit is cleared in the middle of a burst, the
burst will complete before the channel is paused. The DDAR may be written only when RUN is
zero.
DCSRn Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
BIU
STRTB
DONEB
STRTA
DONEA
ERROR
IE
RUN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ?
Bits Name Description
0RUN
Run bit.
This is a control bit and is set by the user to indicate the device address register has been
loaded. No transfer will occur on this channel unless this bit is set. Clearing the RUN bit on
an active channel acts as a pause to that channel. Operation can then be resumed by
again setting the RUN bit.
1IE
Interrupt enable.
This is a control bit and is set by the user to enable interrupts to be passed onto the
interrupt controller. An interrupt is the “OR” of the DONEA, DONEB, and ERROR bits.
2 ERROR
Transfer error bit.
This is a status bit and is set by the DMA controller to indicate a memory error has occurred.
ERROR can generate an interrupt when set if the IE bit is set. ERROR is cleared by software
setting the RUN bit.
3DONEA
Buffer A done.
This is a status bit and is set by the DMA controller to indicate the transfer into or out of buffer
Ahascompleted.DONEAisclearedbywritinga1toitorbysettingtheSTRTAbit.DONEA
can generate an interrupt when set if IE is set.
4STRTA
Buffer A transfer start.
This is a control bit and is written by the user. Setting STRTA causes the buffer A transfer to
begin. This bit is functional only if the RUN bit is set.
5DONEB
Buffer B done.
This is a status bit and is set by the DMA controller to indicate the transfer into or out of buffer
B has completed. DONEB is cleared by writing a 1 to it or by setting the STRTB bit.
DONEB can generate an interrupt when set if IE is set.
6 STRTB
Buffer B transfer start.
This is a control bit and is written by the user. Setting STRTB causes the buffer B transfer
to begin. This bit is functional only if the RUN bit is set.
7BIU
Buffer in use.
This is a status bit and may be read to indicate which buffer (A or B) is active or which
buffer is to be utilized next. This bit is toggled by the DMA controller when DONEA or
DONEB are set. This bit is cleared by all reset sources (hardware, sleep, watchdog, and
software).
0=BufferAinuse.
1=BufferBinuse.
31..8 —
Reserved.
These bits are reserved and read as zeros. Writes to this field have no effect.