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310 SA-1110 Developer’s Manual
Peripheral Control Module
with serial port 2’s UART. When ITR=1, the 4PPM modulator is enabled as well as the HSSP. Note
after one of the two speeds is selected by programming the ITR bit of HSCR0, all further selection
of UART and HSSP options is done by programming the control registers associated with each of
the individual UART and HSSP units.
11.10.6.2 Loopback Mode (LBM)
The loopback mode (LBM) bit is used to enable and disable the ability of the HSSP’s transmit and
receive logic to communicate. When LBM=0, the HSSP operates normally. The transmit and
receive data paths are independent and communicate via their respective pins. When LBM=1, the
output of the transmit serial shifter is directly connected to the input of the receive serial shifter
internally, and (if ITR=1) control of the TXD2 and RXD2 pins is given to the peripheral pin control
(PPC) unit. Note that even though the IrDA standard permits only half-duplex operation, the HSSP
does not restrict the user from transmitting and receiving data at the same time; both are fully
independent units. This function is essential when using the HSSP in loopback mode.
11.10.6.3 Transmit FIFO Underrun Select (TUS)
The transmit FIFO underrun select (TUS) bit is used both to select what action to take as a result of
a transmit FIFO underrun as well as mask or enable the transmit FIFO underrun interrupt.
When TUS=0, transmit FIFO underruns are used to signal the transmit logic that the end of the
frame has been reached. When the transmit FIFO experiences an underrun, the CRC value, which
is calculated continuously on outgoing data, is loaded to the serial shifter and transmitted, followed
by the stop flag and SIP pulse. Also when TUS=0, the transmit FIFO interrupt is masked and the
state of the transmit FIFO underrun (TUR) status bit is ignored by the interrupt controller.
When TUS=1, transmit FIFO underruns are used to signal the transmit logic that the end of the
frame has not yet been reached. When the transmit FIFO experiences an underrun, the CRC value,
which is calculated continuously on outgoing data, is loaded to the serial shifter and transmitted,
followed by the stop flag and SIP pulse. Additionally, when TUS=0, the transmit FIFO underrun
interrupt is masked, causing the state of the transmit FIFO underrun (TUR) status bit to be ignored
by the interrupt controller. Note that programming TUS=0 does not affect the current state of TUR
or the transmit FIFO logic’s ability to set and clear TUR; it only blocks the generation of the
interrupt request.
When TUS=1, transmit FIFO underruns are used to signal the transmit logic that the end of the
frame has not yet been reached and that the rate in which data is supplied to the transmit FIFO is
not sufficient. When the transmit FIFO experiences an underrun, two sequential chips, each
containing zeros (0000), are output by the transmitter to signal an abort condition; next a SIP pulse
is output, followed by a minimum of 16 preambles. Preambles continue to be output until data is
once again available within the transmit FIFO. Additionally, when TUS=1, the transmit FIFO
underrun interrupt is enabled, and whenever TUR is set (one), an interrupt request is made to the
interrupt controller. To change the state of TUS during operation, the user should fill the transmit
FIFO to ensure TUS is not written at the same time that the transmit FIFO underruns.
TUS is useful for ensuring that frames are not prematurely ended due to an unexpected transmit
FIFO underrun. At the start of a frame, the user can configure TUS=1 such that any underrun
signals an abort to the off-chip receiver. Just before the end of the frame, the user can then
configure TUS=0, allowing the remaining data to be output by the transmit logic. The FIFO then
underruns, causing the CRC, stop flag, and SIP to be transmitted.