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SA-1110 Developer’s Manual 7
10.5.1 DRAM Overview...........................................................................................................148
10.5.2 DRAM Timing ...............................................................................................................150
10.5.3 SDRAM Overview.........................................................................................................152
10.5.4 SDRAM Commands .....................................................................................................154
10.5.5 SDRAM State Machine.................................................................................................155
10.5.6 DRAM/SDRAM Refresh ...............................................................................................160
10.5.7 DRAM/SDRAM Self-Refresh in Sleep Mode................................................................161
10.6Static Memory Interface ............................................................................................................162
10.6.1 ROM Interface Overview ..............................................................................................163
10.6.2 ROM Timing Diagrams and Parameters ......................................................................163
10.6.3 SRAM Interface Overview ............................................................................................167
10.6.4 SRAM Timing Diagrams and Parameters ....................................................................167
10.6.5 Variable Latency I/O Interface Overview......................................................................169
10.6.6 Variable Latency I/O Timing Diagrams and Parameters ..............................................169
10.6.7 FLASH Memory Interface Overview.............................................................................172
10.6.8 FLASH Memory Timing Diagrams and Parameters .....................................................172
10.6.9 SMROM Overview........................................................................................................173
10.6.10 SMROM Commands ....................................................................................................173
10.6.11 SMROM State Machine................................................................................................174
10.7PC-Card Overview ....................................................................................................................177
10.7.1 8-, 16-, and 32-Bit Data Bus Operation ........................................................................179
10.7.2 External Logic for PC-Card Implementation.................................................................180
10.7.3 PC-Card Interface Timing Diagrams and Parameters..................................................183
10.8Alternate Memory Bus Master Mode.........................................................................................185
10.9Memory System Examples .......................................................................................................186
10.10SA1110 Memory Configuration Tool .......................................................................................190
11 Peripheral Control Module
11.1Read/Write Interface .................................................................................................................205
11.2Memory Organization................................................................................................................206
11.3Interrupts...................................................................................................................................207
11.4Peripheral Pins..........................................................................................................................208
11.5Use of the GPIO Pins for Alternate Functions...........................................................................209
11.6DMA Controller..........................................................................................................................210
11.6.1 DMA Register Definitions .............................................................................................211
11.6.1.1 DMA Device Address Register (DDARn)...................................................... 211
11.6.1.2 DMA Control/Status Register (DCSRn) ........................................................ 213
11.6.1.3 DMA Buffer A Start Address Register (DBSAn)............................................ 215
11.6.1.4 DMA Buffer A Transfer Count Register (DBTAn).......................................... 216
11.6.1.5 DMA Buffer B Start Address Register (DBSBn)............................................ 216
11.6.1.6 DMA Buffer B Transfer Count Register (DBTBn).......................................... 216
11.6.2 DMA Register List.........................................................................................................217
11.7LCD Controller ..........................................................................................................................219
11.7.1 LCD Controller Operation.............................................................................................220
11.7.1.1 DMA to Memory Interface ............................................................................. 221
11.7.1.2 Frame Buffer ................................................................................................. 221
11.7.1.3 Input FIFO..................................................................................................... 226
11.7.1.4 Lookup Palette .............................................................................................. 226
11.7.1.5 Color/Gray-Scale Dithering ........................................................................... 226