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SA-1110 Developer’s Manual 9
(read/write, maskable interrupt) .................................................................... 250
11.7.11.8 Input FIFO Underrun Upper Panel Status (IUU)
(read/write, maskable interrupt) .................................................................... 250
11.7.11.9 Output FIFO Overrun Lower Panel Status (OOL)
(read/write, maskable interrupt) .................................................................... 250
11.7.11.10 Output FIFO Underrun Lower Panel Status (OUL)
(read only, maskable interrupt) ..................................................................... 250
11.7.11.11 Output FIFO Overrun Upper Panel Status (OOU)
(read/write, maskable interrupt) .................................................................... 250
11.7.11.12Output FIFO Underrun Upper Panel Status (OUU)
(read/write, maskable interrupt) .................................................................... 251
11.7.12 LCD Controller Register Locations...............................................................................252
11.7.13 LCD Controller Pin Timing Diagrams ...........................................................................254
11.8Serial Port 0 – USB Device Controller (UDC) ...........................................................................259
11.8.1 USB Operation .............................................................................................................261
11.8.1.1 Signalling Levels ........................................................................................... 261
11.8.1.2 Connecting the USB to the SA-1110............................................................. 262
11.8.1.3 Bit Encoding.................................................................................................. 263
11.8.1.4 Field Formats ................................................................................................ 264
11.8.1.5 Packet Types ................................................................................................ 265
11.8.1.6 Transaction Formats ..................................................................................... 267
11.8.1.7 SA-1110 UDC Device-Request Commands ................................................. 269
11.8.1.8 Using DMA.................................................................................................... 271
11.8.1.9 Software Control of the SA-1110 UDC.......................................................... 271
11.8.1.10SA-1110 USB Example Code....................................................................... 278
11.8.2 SA-1110 UDC Register Definitions...............................................................................278
11.8.3 UDC Control Register (UDCCR) ..................................................................................279
11.8.3.1 UDC Disable (UDD) ...................................................................................... 280
11.8.3.2 UDC Active (UDA)......................................................................................... 280
11.8.3.3 Resume Interrupt Mask (RESIM).................................................................. 280
11.8.3.4 Endpoint 0 Interrupt Mask (EIM) ................................................................... 281
11.8.3.5 Receive Interrupt Mask (RIM) ....................................................................... 281
11.8.3.6 Transmit Interrupt Mask (TIM)....................................................................... 281
11.8.3.7 Suspend Interrupt Mask (SUSIM) ................................................................. 282
11.8.3.8 Reserved/B5 ................................................................................................. 282
11.8.4 UDC Address Register (UDCAR).................................................................................282
11.8.5 UDC OUT Maximum Packet Register (UDCOMP).......................................................283
11.8.6 UDC IN Maximum Packet Register (UDCIMP).............................................................284
11.8.7 UDC Endpoint 0 Control/Status Register (UDCCS0) ...................................................284
11.8.7.1 OUT Packet Ready (OPR)............................................................................ 285
11.8.7.2 IN Packet Ready (IPR).................................................................................. 285
11.8.7.3 Sent Stall (SST) ............................................................................................ 286
11.8.7.4 Force Stall (FST)........................................................................................... 286
11.8.7.5 Data End (DE)............................................................................................... 286
11.8.7.6 Setup End (SE) ............................................................................................. 286
11.8.7.7 Serviced OPR (SO)....................................................................................... 286
11.8.7.8 Serviced Setup End (SSE)............................................................................ 286