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272 SA-1110 Developer’s Manual
Peripheral Control Module
4. Resume Interrupt:
a. Software should be able to write a 1, then a 0, to the RESIM bit (bit 2) of UDCCR to clear
the internal suspend state machine.
b. Software may also write a 0 to the SUSIM bit (bit 6) of the UDCCR to unmask the
suspend interrupt.
c. Software should be able to write a 1 to the RESIR bit (bit 4) of the UDCSR to clear the
resume interrupt.
5. Endpoint 0 Interrupt:
a. Get the command packet from the FIFO.
b. Parse the command.
c. Setup the endpoint to respond to the command.
6. Endpoint 1 Interrupt:
a. Check that a complete packet is received.
b. Check for any errors.
c. Empty the remaining bytes out of the FIFO.
d. Setup the endpoint to get ready for a new packet of data.
7. Endpoint 2 Interrupt:
a. Check that a complete packet was transmitted.
b. Check for any errors.
c. Setup the endpoint to transmit a new packet of data.
11.8.1.9.2 Endpoint Operation
When a USB interrupt is received, software is vectored to its USB ISR. Software first clears the
appropriate interrupt register USIR0 bit. It then vectors to its appropriate endpoint process routine.
Initially only EP0 interrupt is enabled on power-up or after reset. The other interrupts are enabled
as required by the SET CONFIG command.
As stated in Section 11.8.2 it is necessary to verify the effects of any writes to registers before
continuing, e.g., loop on every write until the write takes place.
Case 1: EP0 Control Read (e.g. Get Descriptor)
1. At the beginning of the program, software initializes the internal state machine to
WAIT_FOR_SETUP.
2. Host sends a SETUP command.
3. SA-1110 UDC generates an EP0 Interrupt.
4. The software then determines the UDCCS0-OPR bit is set - 0000 0001b.
5. This indicates that a new OUT packet is in the EP0 Buffer identifying a SETUP transaction. To
help track this, software uses its state machine, which is currently WAIT_FOR_SETUP. This
is to ensure fast software waits until all 8 bytes of the setup are in the FIFO before reading the
data.
6. Software reads into a local buffer an amount of data from the UDCD0 Data Register FIFO as
specified by UDCWC-WC bits. To read the data: a) read the UDCWC-WC bits, b) read
UDCCD0, c) re-read the UDCWC-WC bits, and d) keep reading UDCCD0 followed by the