Filter
Top Products
320 SA-1110 Developer’s Manual
Peripheral Control Module
Note: A question mark (?) signifies that the Reset value of that bit is undefined when the processor has
completed its reset cycle.
11.10.11 HSSP Status Register 1
HSSP status register 1 (HSSR1) contains flags that indicate when the receiver is synchronized, the
transmitter is active, the transmit FIFO is not full, the receive FIFO is not empty, and when an
end-of-frame, CRC error, or underrun error has occurred. All bits within HSSR1 are read-only and
noninterruptible.
0h 8004 0074 HSSR0 Read/Write and Read-Only
7 6 5 4 3 2 1 0
Reserved FRE RFS TFS RAB TUR
EIF
Reset
0 0 ? 0 0 ? ? ?
Bits Name Description
0EIF
End/error in FIFO (read-only).
0 – Bits 8–10 are not set within any of the eight bottom entries of the receive FIFO. Receive
FIFO DMA service requests are enabled.
1 – One or more tag bits (8 – 10) are set within one or more of the bottom eight entries of
the receive FIFO. Request interrupt, disable receive FIFO DMA service requests.
1TUR
Transmit FIFO underrun.
0 – Transmit FIFO has not experienced an underrun.
1 – Transmit logic attempted to fetch data from transmit FIFO while it was empty; interrupt
request signalled if not masked (if TUS=1).
2RAB
Receiver abort.
0 – No abort has been detected for the incoming frame.
1– Abort detected during receipt of incoming frame. Two or more chips containing no
pulses (0000), or invalid chips not contained within the stop flag, detected on receive pin.
EOF bit set in receive FIFO next to last piece of “good” data received before the abort,
interrupt requested.
3TFS
Transmit FIFO service request (read-only).
0 – Transmit FIFO is more than half-full (nine or more entries filled) or transmitter disabled.
1 – Transmit FIFO is half-full or less (eight or fewer entries filled) and transmitter operation
is enabled. DMA service request signalled; interrupt request signalled if not masked (if
TIE=1).
4RFS
Receive FIFO service request (read-only).
0 – Receive FIFO contains 11 or fewer entries of data or receiver disabled.
1 – Receive FIFO is two- to three-fifths full (contains 9, 10, 11, or 12 entries of data) or
more, and receiver operation is enabled. DMA service request signalled; interrupt request
signalled if not masked (if RIE=1).
5FRE
Framing error.
0 – No framing errors encountered in the receipt of this data.
1 – Framing error occurred; preamble followed by something other than another preamble
or start flag, request interrupt.
7..6 — Reserved.