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SA-1110 Developer’s Manual 411
Debug Support 15
Due to the integration level of the Intel
®
StrongARM
*
SA-1110 Microprocessor (SA-1110), many
functions are not directly visible on the external pins. Therefore, some basic debug facilities are
provided that are not present on the Intel StrongARM SA-110 Microprocessor (SA-110). These
facilities are in the form of breakpoints that provide the user with the ability to stop execution after
seeing a specific reference in either the instruction or data streams. Execution then proceeds to an
exception routine during which the user may examine the internal state of the machine. The
instruction and data breakpoint facilities are described in this chapter. The breakpoints are enabled
through additions to coprocessor 15.
15.1 Instruction Breakpoint
The instruction breakpoint allows the user to stop the processor execution after the execution of an
instruction at a selected address. This address is programmed into the instruction breakpoint
address and control register (IBCR). This register is 32 bits wide and contains the address value for
the breakpoint, and a bit to enable the breakpoint. Bit 0 is the enable bit. When set, this bit enables
the breakpoint and when cleared, it disables the breakpoint. Bit 1 is reserved and has no effect
when written. Bits 31..2 are compared against the fetch address to qualify the breakpoint. When the
breakpoint is enabled, the SA-1110 executes until the instruction at this address is fetched and the
fetch address equals the program counter (ignoring bits 0 and 1 of the address). At this point, the
processor takes a prefetch abort exception. The interrupt routine must examine R14 (the saved
program counter) to determine if the exception was caused by the breakpoint.
The IBCR is loaded by way of coprocessor 15, register 14. Access to this register is privileged. See
the Section 6.1, “Internal Coprocessor Instructions” on page 6-55 fordetailsontheformatofthe
instruction used to access the IBCR.
15.2 Data Breakpoint
The data breakpoint allows the user to stop the processor execution after a load or store operation
to a particular address. The data breakpoint address is programmed into the data breakpoint address
register (DBAR) and is a full 32-bit value (to permit breakpoints on byte accesses).
For stores, the breakpoint condition may also be programmed to include a particular data pattern as
well as the reference address. The data value is programmed by way of the data breakpoint value
register (DBVR) and the data breakpoint mask register (DBMR). The DBVR is a 32-bit register
containing the value against which the store data is compared. The data value can be further
qualified through the data breakpoint mask register (DBMR). The DBMR is a 32-bit register
containing mask information indicating which bits in the store data should be compared against the
DBMR. A 1 in a particular bit position in the DBMR indicates that bit in the DBVR should be
compared against the store data to qualify the breakpoint. To cause a breakpoint on a store data
value, the address breakpoint must also be enabled, otherwise, no breakpoint will occur.
Breakpoints on loads are permitted only through an address match. Breakpoints on load address,
store address, and store data are enabled and disabled through the data breakpoint control register
(DBCR). A single bit is defined for each action. When a breakpoint is taken, the processor takes a
data abort exception and sets bit 9 in the fault status register (FSR). The DBAR, DBVR, and
DBMR are loaded by way of coprocessor 15, register 14. Access to this register is privileged.