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SA-1110 Developer’s Manual 321
Peripheral Control Module
11.10.11.1 Receiver Synchronized Flag (RSY) (read-only, noninterruptible)
The receiver synchronized (RSY) flag is a read-only bit that is set when the receiver is
synchronized with the incoming data stream, and is cleared when the receive logic is in hunt mode
(looking for the preamble to achieve byte and frame synchronization), or the receiver is disabled
(RXE=0). This bit does not request an interrupt.
11.10.11.2 Transmitter Busy Flag (TBY) (read-only, noninterruptible)
The transmitter busy (TBY) flag is a read-only bit that is set when the transmitter is actively
transmitting a frame (address, control, data, CRC, start or stop flag), and is cleared when the
transmitter is idle (transmitting preambles) or the transmitter is disabled (TXE=0). This bit does not
request an interrupt.
11.10.11.3 Receive FIFO Not Empty Flag (RNE) (read-only, noninterruptible)
The receive FIFO not empty flag (RNE) is a read-only bit that is set whenever the receive FIFO
contains one or more bytes of valid data and is cleared when it no longer contains any valid data.
This bit can be polled when using programmed I/O to remove remaining bytes of data from the
receive FIFO because DMA service and CPU interrupt requests are made only when 12, 11, 10, or
9 bytes reside within the FIFO. Data will remain after each service request as well as at the end of a
frame. This bit does not request an interrupt.
11.10.11.4 Transmit FIFO Not Full Flag (TNF) (read-only, noninterruptible)
The transmit FIFO not full flag (TNF) is a read-only bit that is set whenever the transmit FIFO
contains one or more entries that do not contain valid data and is cleared when the FIFO is
completely full. This bit can be polled when using programmed I/O to fill the transmit FIFO over
its halfway mark. This bit does not request an interrupt.
11.10.11.5 End-of-Frame Flag (EOF) (read-only, noninterruptible)
The end-of-frame flag (EOF) is set when the last byte of data within a frame (including aborted
frames) resides within the bottom entry of the receive FIFO.
The receive FIFO contains three tag bits (8, 9, and 10) that are not directly readable. The 8th bit is
set at the top of the FIFO whenever the last byte within a frame is moved from the receive serial
shifter to the top of the receive FIFO. This tag travels along with the last data value as it moves
down the FIFO. Each time a data value is transferred to the bottom of the FIFO (caused by a read
of the previous value), the state of the tag bit is moved from the FIFO to the EOF bit in the status
register. Whenever EOF is set within the bottom eight entries of the receive FIFO, EIF is set within
HSSR0, an interrupt is signalled, and the receive FIFO DMA request is disabled. After the
end/error in FIFO (EIF) status bit is set, the user should always read HSSR1 first to check EOF
before reading the data value from HSDR because EOF corresponds to the current data byte at the
bottom of the receive FIFO and is updated each time data is removed from the FIFO.
11.10.11.6 CRC Error Flag (CRE) (read-only, noninterruptible)
The CRC error flag (CRE) is set when the CRC value calculated by the receive logic does not
match the CRC value contained within the incoming serial data stream.