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72 SA-1110 Developer’s Manual
Clocks
• To supply external clock signals from a 3.3-V supply, drive signals with open collector or
tristateable drivers. Set high level with 3.3 K from 3.3 V to the output and 1.3 K from the
output to ground.
• To supply external clock signals from a 1.5-V supply, drive signals with open collector or
tristatable drivers. Set high level with 1.5 K from 1.5 V to the output and 2.7 K from output to
ground. This solution may be preferred in portable applications that turn off the 1.5-V supply
in sleep mode because this would eliminate the current through the resistors in sleep mode.
The two pairs of crystal pins are located close to each other on the processor. This arrangement is
advantageous when there are crystals connected to the pins because the low signal swings and slow
edges result in limited noise coupling between the pins. If one of the crystals is replaced by an
independent signal source and the other is not, some degradation of the remaining crystal oscillator
performance can result due to increased noise coupling. If only one crystal is being used, this effect
can be reduced by limiting the speed of the edge rate on the pin driven by the independent source.
If the PXTAL or TXTAL pin is driven above the voltage indicated, there will be no permanent
damage to the processor for pin voltages less than 2.5 V. However, ESD diodes on these pins will
attempt to clamp the voltage at approximately 1.5 V. The clamping action results in significant
noise injected into an internally generated supply used by several sensitive circuits on the
processor. Consequently, driving this pin higher than the 1 V limit can result in unpredictable
operation not obviously connected with the crystal pins. It is advised to not drive the crystal pins
higher than 1 V even if there is no obvious side effect.
Note: In every system, there must be a provision for both a 3.6864-MHz and a 32.768-kHz source either
from an external oscillator or a crystal.
8.4 Clocking During Test
If TCK_BYP is high, then the PLLs and oscillators are not used and the high-speed core clock is
supplied externally on the TESTCLK pin. This mode is for testing only and is not supported for
standard operation.