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SA-1110 Developer’s Manual 149
Memory and PC-Card Control Module
Table 10-8 shows the DRAM row/column address multiplexing. For each row size, RAS time to
CAS time address bit changes only occur if they are required; all other bits (including A 25 and
A 9:0 bits not shown here) remain driven by the corresponding internal address bits throughout the
transfer. Column address sizes of 12, 11, 10, 9, and 8 are supported if three conditions are met:
• The row address is larger than or same size as the column address
• The combined row and column address size does not exceed the maximum bank size that can
be implemented with 4-bit DRAM chip organizations
• The combined row and column address size does not exceed the 128-Mbyte architectural bank
size. The user does not explicitly specify the column address size; connecting the address lines
to the DRAM devices as shown allows proper addressing. The column address multiplexing
differs for 16-bit (shown in parentheses) and 32-bit data busses.
When accessing SDRAM, only DRA[9:0] (and possibly DRA11) are used for column addressing.
DRA10 is driven with "0" or "1" to help encode the READ, READAP, WRIT, and WRITEAP
commands. DRA[14:12] (and possibly DRA11) maintain the upper bits of the row address, which
includes the SDRAM internal bank number. During SDRAM configuration, in between any read or
write accesses, all of the address pins are used to transfer the MRS command.
DRAx = SA-1110 DRAM interface address pin, A[24:10] = DRA[14:0]
IAx = Internal address bit
IAx = Internal address bit driven during CAS time to specify internal bank number (SDRAM only)
Note: At RAS time, all address pins, A[25:0], are driven by the same bit numbers of the internal address.
Thus, for a given number of MDCNFG:DRAC0,2 programmed row address bits, higher bit
numbers (A 25) can be used by connecting them to the appropriate DRAM address pins. However,
this causes the corresponding internal address bits (IA25) to be used during both RAS and CAS
and creates non-addressable locations in the physical memory. If these higher row address bit
numbers must be used, column addresses must be limited to a maximum of 8 bits (9 if using a
16-bit data bus). In general, DRAM that utilize fewer than these 8 column address bits can be used,
Table 10-8. DRAM or SMROM Row/Column Address Multiplexing
Number of
Row Address
Bits(including
SDRAM Bank
selects)
DRAM or
SMROM
Address Pins
at RAS Time
DRAM or SMROM Address Pins at CAS Time
DRA[14:0] =
IA[24:10]
DRA14
DRA13
(BA0)
DRA12
(BA1)
DRA11
(BA)
DRA10
(AP)
DRA9 DRA8 DRA 7:0
15 bits IA[24:10] IA24 IA23 IA22
IA21
(IA26)
IA20
IA26
(IA25)
IA25
(IA9)
IA[9:2]
(IA[8:1])
14 bits
IA[24:10] IA24 IA23 IA22 IA21 IA20
IA25
(IA24)
IA24
(IA9)
IA[9:2]
(IA[8:1])
13 bits
IA[24:10] IA24 IA23 IA22 IA21
IA25
(IA24)
IA24
(IA23)
IA23
(IA9)
IA[9:2]
(IA[8:1])
12 bits
IA[24:10] IA24 IA23 IA22
IA25
(IA24)
IA21
IA24
(IA23)
IA23
(IA22)
IA22
(IA9)
IA[9:2]
(IA[8:1])
11 bits
IA[24:10] IA24 IA23 IA22 IA21
IA23
(IA22)
IA22
(IA21)
IA21
(IA9)
IA[9:2]
(IA[8:1])
10 bits
IA[24:10] IA24 IA23 IA22 IA21 IA20
IA21
(IA20)
IA20
(IA9)
IA[9:2]
(IA[8:1])
9bits
IA[24:10] IA24 IA23 IA22 IA21 IA20 IA19
IA19
(IA9)
IA[9:2]
(IA[8:1])