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174 SA-1110 Developer’s Manual
Memory and PC-Card Control Module
• Power-Down (PWRDN)
• Exit Power-Down (PWRDNX)
• Mode Register Set (MRS)
• Row Activate (ACT)
• Read (READ)
• Burst Stop (STOP)
• No Operation (NOP)
Table 10-11 shows the SMROM interface commands.
10.6.11 SMROM State Machine
Figure 10-17 illustrates all possible SMROM controller states and transitions. Many of the states
are named after the SMROM commands with which they are coincident: they have a fixed duration
of one SMROM (SDCLK 0) cycle. Transitions from the other states are determined by the overall
memory controller state and a few SMROM/SDRAM power-down/self-refresh status/control bits.
Most of the states and transitions may involve multiple SMROM devices. Only those states shown
below the "Idle" state involve a single SMROM row. If none of the labeled transitions have their
conditions satisfied and no default transition is indicated, the current state is maintained for at least
one more SMROM cycle.
Hardware or sleep reset causes the SMROM state machine to enter the "Idle" state. Upon hardware
or sleep reset, the SA-1110 is compatible with the following SMROM default mode registers
settings: RAS latency of 2 external SDCLK 0 cycles, CAS latency of 5 external SDCLK 0 cycles,
burst length of 4, and sequential burst addressing. However, the mode registers must be written
prior to attempting bursts (caches or read buffer enabled). Writes to the SMCNFG register instigate
one or two MRS commands (to one or two bank pairs of SMROM). These MRS commands always
change the burst length to 8; RAS latency and CAS latency may change according to SMCNFG
bits. As required to ensure high impedance on SMROM data outputs, the SA-1110 holds nWE,
SDCKE 0 (for SMROM_EN = 1), and nOE high during power-up.
Table 10-11. SMROM Command Encoding
Command
SA-1110 Pins
SDCKE
(at
clock
n-1)
SDCKE
(at
clock
n)
ncs[3:0] nSDRAS nSDCAS nWE nOE DRA12-0
PWRDN1011 1 14’b1111 x
PWRDNX 0111 1 14’b1111 x
MRS 1 x 0 0 0 0 1
Mode
(DRA[12:7] = 6’b0
DRA 6 = {RL},
DRA[5:3] = {CL}
DRA[2:0] = 3’b010)
ACT 1 x 0 0 1 1 1 Row
READ1x01 0 10 Column
STOP1x00 1 01 x
NOP1x1x x xx x
NOP 1 x 0 1 1 1 1 x