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SA-1110 Developer’s Manual 277
Peripheral Control Module
Case 5: EP0 No Data Command
1. At the beginning of the program, software initializes the internal state machine to
WAIT_FOR_SETUP.
2. Host sends a SETUP command.
3. SA-1110 UDC generates an EP0 Interrupt.
4. The software then determines the UDCCS0-OPR is set - 0000 0001b.
5. This indicates that a new OUT packet is in the EP0 Buffer identifying a SETUP transaction. To
help track this, software uses its state machine which is currently WAIT_FOR_SETUP.
6. Software reads into a local buffer an amount of data from the UDCD0 Data Register FIFO as
specified by UDCWC-WC bits. To read the data: a) read the UDCWC-WC bits, b) read
UDCCD0, c) re-read the UDCWC-WC bits, and d) keep reading UDCCD0 followed by the
UDCWC-WC bits until the UDCWC-WC bits decrement.
7. When parsing the data which is now in the buffer, software may see that this is a no-data type
of command. Software will execute the command and sets its internal state machine to
WAIT_FOR_STATUS. The software clears the UDCCS0-OPR bit and sets the UDCCS0-DE
bit by simultaneously writing to the UDCCS0-SO and UDCCS0-DE bits. The UDCCS0
register should now be 0001 0000b.
8. Return from interrupt.
9. When the Host executes the STATUS stage, the SA-1110 UDC clears the UDDCS0-IPR bit
causing an interrupt.
10. Upon entering the ISR routine, software sees that the UDCCS0 register is 0000 0000b, then
examines its internal state machine which is WAIT_FOR_STATUS. When it sees the
UDCCS0 is all zeros, it knows the STATUS stage was sent, and it must transfer its internal
state machine back to WAIT_FOR_SETUP.
Case 6: EP1 Data Receive (Bulk-OUT)
1. At this point in the program, software has received a SETUP VENDOR command setting up
an EP1-BULK-OUT transaction. Software has configured the DMA engine and enabled the
EP1 interrupt to feed the DMA engine to handle the data.
2. During the SETUP VENDOR command, software sets up the DMA engine. Software
determines the amount of data to be transferred and if the amount is less than the maximum
packet value indicated in the UDCIMP register, software reprograms the UDCIMP register
with the byte amount to be transferred (bytes –1). For the DMA engine channel used, software
determines the current active data buffer and provides the DMA the current data buffer pointer.
3. The Host sends a BULK-OUT.
4. The SA-1110 UDC reads the data into the UDCDR FIFO and generates an EP1 interrupt.
5. The software checks to see that the UDCCS1-RPC bit is set to 1 to insure validity of the other
register bits.
6. The software data buffer index is incremented by the amount of bytes transferred. This is
obtained from the receive DMA channel.
7. If the UDCCS1-RPE bit is a 0 indicating no errors, the UDCCS1-RNE bit is checked to see if
it is set to 1, indicating that there is remaining data in the FIFO which software needs to
retrieve. It then moves any remaining data from the FIFO into the data buffer.
8. The DMA engine is restarted, i.e. repeat step 2, and the UDCCS1-RPC bit is cleared.