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SA-1110 Developer’s Manual 135
Memory and PC-Card Control Module
29 KAPD
SDRAM/SMROM clock pin (SDCLK [2:0]) auto-power-down enable.
If KAPD=1, each of the clock pins (SDCLK 0 for SMROM, SDCLK 1 for SDRAM bank pair
0/1, and SDCLK 2 for SDRAM bank pair 2/3) will automatically deassert (stop running)
whenever none of the corresponding banks is being accessed. EAPD and KAPD must be
written to the same value. See Figure 10-5 and Figure 10-17. Auto-power-down must not
be enabled until all other SDRAM/SMROM hardware or sleep reset procedures have been
completed. See Section 10.2.1.
30 — Reserved.
31 SLFRSH
SDRAM self-refresh control/status.
It is the control/status bit for entering and exiting SDRAM self-refresh and it is automatically
set upon a hardware or sleep reset.
SLFRSH can be set by program to force a self-refresh command. E1PIN does not have to
be cleared. The appropriate clock run bits (K1RUN and/or K2RUN) must remain set until
SDRAM has entered self-refresh and must be set prior to exiting self-refresh (clearing
SLFRSH). Also, auto-power-down must be disabled (EAPD=KAPD=0) to ensure
power-down-exit upon subsequent clearing of SLFRSH. This capability should be used
with extreme caution because the resulting state prohibits automatic transitions for any
commands.See Section 10.5.5.
Clearing SLFRSH is a part of the hardware or sleep reset procedure for SDRAM. See
Section 10.2.1.
0h A000 001C MDREFR Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLFRSH
Reserved
KAPD
EAPD
Reserved
K2DB2
K2RUN
Reserved
Reserved
K1DB2
K1RUN
E1PIN
Reserved
K0DB2
K0RUN
E0PIN
DRI11
DRI10
DRI9
DRI8
DRI7
DRI6
DRI5
DRI4
DRI3
DRI2
DRI1
DRI0
TRASR3
TRASR2
TRASR1
TRASR0
Reset 1 ? 0 0 ? 1 0 ? ? 1 0 0 ? 1 * * ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
* Upon hardware or sleep reset, K0RUN and E0PIN are set to the value of the SMROM_EN pin.
(Sheet 4 of 4)
Bits Name Description