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SA-1110 Developer’s Manual 33
Functional Description
SDCLK[2:0] OCZ SDRAM and/or SMROM clock.
SDCLK 0 should be connected to the clock (CLK) pins of SMROM.
SDCLK 1 and SDCLK 2 should be connected to the clock pins of SDRAM in bank
pairs 0/1 and 2/3, respectively. They are driven by either the internal memory
controller clock (CPU clock divided by 2) or the memory controller clock divided by
2 (CPU clock divided by 4).
All SDCLK pins are held low during sleep mode and start running at CPU clock
divide by 4 upon any reset (including sleep-exit).
The memory controller provides control register bits for clock division and disable
of each SDCLK pin. However, SDCLK 0 cannot be disabled via program if static
memory bank 0 (boot space) is configured for synchronous mask ROM
(SMROM_EN = 1).
RD/nWR OCZ Read/write direction control for memory and PCMCIA data bus (D[31:0]). This
signal is applicable to all memory bus and PCMCIA transfers.
For reads (RD/nWR = 1), system-level bus transceivers or directly connected
memory devices should drive D[31:0].
For writes (RD/nWR = 0), the SA-1110 will drive D[31:0].
nPOE OCZ PCMCIA output enable. This signal is an output and is used to perform reads from
memory and attribute space.
nPWE OCZ PCMCIA write enable. This signal is an output and is used to perform writes to
memory and attribute space.
nPIOW OCZ PCMCIA I/O write. This signal is an output and is used to perform write
transactions to the PCMCIA I/O space.
nPIOR OCZ PCMCIA I/O read. This signal is an output and is used to perform read
transactions from the PCMCIA I/O space.
nPCE[2:1] OCZ PCMCIA card enable. These signals are output and are used to select a PCMCIA
card. nPCE 2 enables the high-byte lane and nPCE 1 enables the low-byte lane.
nIOIS16 IC I/O Select 16. This signal is an input and is an acknowledgment from the PCMCIA
card that it can perform 16-bit I/O data transfers.
nPWAIT IC PCMCIA wait. This signal is an input and is driven low by the PCMCIA card to
extend the duration of transfers to/from the SA-1110.
PSKTSEL OCZ PCMCIA socket select. This signal is an output and is used by external steering
logic to route control, address, and data signals to one of the PCMCIA sockets.
When PSKTSEL is low, socket zero is selected. When PSKTSEL is high, socket
one is selected. This signal has the same timing as the address lines.
nPREG OCZ PCMCIA register select. This signal is an output and indicates that, on a memory
transaction, the target address is attribute space. This signal has the same timing
as address.
L_DD[7:0] OCZ LCD controller display data.
L_FCLK OCZ LCD frame clock.
L_LCLK OCZ LCD line clock.
L_PCLK OCZ LCD pixel clock.
L_BIAS OCZ LCD ac bias drive.
TXD_C OCZ CODEC transmit.
RXD_C IC CODEC receive.
Table 2-1. Signal Descriptions (Sheet 2 of 4)
Name Type Description