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250 SA-1110 Developer’s Manual
Peripheral Control Module
11.7.11.6 Input FIFO Underrun Lower Panel Status (IUL) (read/write, maskable
interrupt)
The input FIFO underrun lower panel status (IUL) bit is set when the lower panel’s input FIFO is
completely empty and the LCD’s pixel unpacking logic attempts to fetch data from the FIFO. It is
cleared by writing a 1 to the bit. This bit is used only in dual-panel mode (SDS=1). When this bit is
set, an interrupt request is made to the interrupt controller if it is unmasked (ERM=0).
11.7.11.7 Input FIFO Overrun Upper Panel Status (IOU) (read/write, maskable
interrupt)
The input FIFO overrun upper panel status (IOU) bit is set when the LCD’s DMA channel 1
attempts to place data into the upper panel’s input FIFO after it has been completely filled. It is
cleared by writing a 1 to the bit. This bit is used in single-panel mode (SDS=0) and dual-panel
mode (SDS=1). When this bit is set, an interrupt request is made to the interrupt controller if it is
unmasked (ERM=0).
11.7.11.8 Input FIFO Underrun Upper Panel Status (IUU) (read/write, maskable
interrupt)
The input FIFO underrun upper panel status (IUU) bit is set when the upper panel’s input FIFO is
completely empty and the LCD’s pixel unpacking logic attempts to fetch data from the FIFO. It is
cleared by writing a 1 to the bit. This bit is used in single-panel mode (SDS=0) and dual-panel
mode (SDS=1). When this bit is set, an interrupt request is made to the interrupt controller if it is
unmasked (ERM=0).
11.7.11.9 Output FIFO Overrun Lower Panel Status (OOL) (read/write, maskable
interrupt)
The output FIFO overrun lower panel status (OOL) bit is set when the LCD’s dither logic attempts
to place data into the lower panel’s output FIFO after it has been completely filled. It is cleared by
writing a 1 to the bit. This bit is used only in dual-panel mode (SDS=1). When this bit is set, an
interrupt request is made to the interrupt controller if it is unmasked (ERM = 0).
11.7.11.10 Output FIFO Underrun Lower Panel Status (OUL) (read only,
maskable interrupt)
The output FIFO underrun lower panel status (OUL) bit is set when the lower panel’s output FIFO
is completely empty and the LCD’s data pin driver logic attempts to fetch data from the FIFO. It is
cleared by writing a 1 to the bit. This bit is used only in dual-panel mode (SDS=1). When this bit is
set, an interrupt request is made to the interrupt controller if it is unmasked (ERM=0).
11.7.11.11 Output FIFO Overrun Upper Panel Status (OOU) (read/write,
maskable interrupt)
The output FIFO overrun upper panel status (OOU) bit is set when the LCD’s dither logic attempts
to place data into the upper panel’s output FIFO after it has been completely filled. It is cleared by
writing a 1 to the bit. This bit is used in single-panel mode (SDS=0) and dual-panel mode (SDS=1).
When this bit is set, an interrupt request is made to the interrupt controller if it is unmasked
(ERM=0).