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SA-1110 Developer’s Manual 263
Peripheral Control Module
Caution: Never put the SA-1110 into Sleep mode while the USB cable is connected to the SA-1110 UDC.
During Sleep mode, the SA-1110 UDC’s registers are reset, and therefore (after the SA-1110 is
brought out of Sleep mode) the SA-1110 UDC will not respond to its Host-assigned address.
Note: The pull-down resisters in Figure 11-14 are not called for in USB Specification Version 1.1, but
they are necessary for proper operation the SA-1110 UDC.
Figure 11-14. Connecting the USB to the SA-1110 UDC
11.8.1.3 Bit Encoding
USB uses Nonreturn–To–Zero Inverted (NRZI) encoding of data bits with the bit clocks, i.e., data
bits and the bit clock are encoded together within the same signal. A “zero” is represented by a
transition, and a “one” is represented by no transition. Each time a “zero” occurs, the receiver logic
synchronizes its baud clock to the incoming data. To ensure that the receiver is periodically
synchronized, any time six consecutive “ones” are detected, a “zero” is automatically inserted by
the transmitter. This procedure is known as “bit stuffing”. So, “bit stuffing” forces a transition on
the incoming data stream at least once every seven bit-times to guarantee locking of the receiver’s
baud clock. The receiver logic automatically detects “stuffed” bits and removes them. “Bit
stuffing” is enabled for an entire packet beginning when Start Of Packet is detected and ending
when End Of Packet is detected, i.e., “bit stuffing” is enabled from the start of the Sync field all the
way through the end of the CRC field). Figure 11-15 shows the NRZI encoding of the data byte
0b1101 0010.
A8036-01
Intel® StrongARM*
SA-1110 Processor
Universal Serial
Bus
USB GND
UDC–
UDC+
USB 5V
UDC–
UDC+
GPIOn
470K
1.5K
470K
5V to 3.3V