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210 SA-1110 Developer’s Manual
Peripheral Control Module
11.6 DMA Controller
The DMA controller consists of six independent DMA channels. Each channel can be configured
to service any of the serial controllers. Two channels are required to service a full-duplex serial
controller. The DMA controller is intended to relieve the processor of the interrupt overhead in
servicing these ports with programmed I/O. If desired, any or all peripherals may be serviced with
programmed I/O instead of DMA. Each peripheral is capable of requesting processor service
through its own interrupt lines or through a DMA request.
The DMA controller consists of a set of configuration and control registers for each channel and a
common data transfer engine which services the active channel. Channels are serviced in a fixed
priority sequence if the DMA receives multiple requests. Each channel is serviced in increments of
that device’s burst size and delivered in the granularity of that device’s port width (byte or
half-word). The burst size and port width for each device is programmed in the channel registers
and is based on the device’s FIFO depth and bandwidth needs. When multiple channels are actively
executing, each channel is serviced with a burst of data after which the DMA controller may
perform a context switch to another active channel. The DMA controller performs context switches
based on whether a channel is active, whether its target device is currently requesting service (the
FIFO is half-empty), and where that channel lies in the priority scheme. Channels are serviced in a
fixed priority with channel 0 being the highest and channel 5 being the lowest. A context switch
may occur when a channel completes a command or when a particular burst (portion of a transfer)
has been completed. For example, if the FIFO in a particular transmit serial controller is full and
cannot accept more data, that channel may be switched out of the active context in favor of another
channel which is requesting service. An active channel may actually go idle many times as the
device is serviced.
Data transfers are performed between a device (one of the serial controllers) and memory (ROM,
RAM, Flash, SRAM, or DRAM). DMA transfers to and from PCMCIA space are not permitted.
DMA write transfer attempts to ROM and Flash memory are not prevented by the DMA controller
but will not complete successfully due to the read-only characteristics of ROM and the DMA
controller not supporting specific write control sequences required by Flash memory technologies,
respectively. During a peripheral write, a burst of data is read from memory as words into a transfer
buffer inside the DMA controller. The data from the transfer buffer is then written to the device
according to the device’s port width and the state of the endian bit (E) in the DMA device address
register (DDARn). During a peripheral read, data is read from the device according to the device’s
port width, the data is accumulated in a transfer buffer inside the DMA controller, and then the
transfer buffer’s contents are sent to memory as words. The order of the bytes inside that word is
determined again by the endian bit (E).
The control registers for each channel include two starting address registers and two transfer count
registers. These registers must be programmed by the system at the start of the transfer. The
registers control two rotating buffers for use during a transfer; these buffers, designated buffer A
and buffer B, are actually user defined independent regions of memory which contain the source
data to be written to a device for a DMA write transfer or these two buffers are the target region of
memory where data read from a device are stored from a DMA read transfer operation. Buffer A
and buffer B can be chained together so that when a transfer to (or from) one buffer completes, the
transfer to (or from) the other begins immediately. By interrogating the status information in the
channel control/status register, the user can safely update the address pointer and transfer count of
theinactivebuffer.