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SA-1110 Developer’s Manual 251
Peripheral Control Module
11.7.11.12 Output FIFO Underrun Upper Panel Status (OUU) (read/write,
maskable interrupt)
The output FIFO underrun upper panel status (OUU) bit is set when the upper panel’s output FIFO
is completely empty and the LCD’s data pin driver logic attempts to fetch data from the FIFO. It is
cleared by writing a 1 to the bit. This bit is used in single-panel mode (SDS=0) and dual-panel
mode (SDS=1). When this bit is set, an interrupt request is made to the interrupt controller if it is
unmasked (ERM=0).
The following table shows the location of the status and flag bits in LCSR. For reserved bits, writes
are ignored and reads return zero. Set status bits should be cleared by software before enabling both
the LCD controller and interrupt controller.
Note: When the interrupt to the LCD Controller is first unmasked by programming ICMR: 12 to 1, an
unwanted interrupt is immediately generated. To avoid this interrupt, LCSR: LDD (LCD disable
done flag) should be cleared (by writing a 1 to it) before unmasking ICMR: 12.
0h B010 0004 LCSR: LCD Status Register Read/Write and Read-Only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
OUU
OOU
OUL
OOL
IUU
IOU
IUL
IOL
ABC
BER
BAU
LDD
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(Sheet 1 of 2)
Bits Name Description
0LDD
LCD disable done status.
0 – LCD has not been disabled and the last active frame completed.
1 – LCD has been disabled and the last active frame has just completed.
1BAU
Base address update flag (read-only).
0 – Base address has been written and has not yet been transferred to the current address
register.
1 – Base address has been transferred to the current address register, triggered either by
enabling the LCD or when the current address pointer equals the end address value
calculated by the LCD.
2BER
Bus error status.
0 – DMA has not attempted an access to reserved/nonexistent memory space.
1 – DMA has attempted an access to a reserved/nonexistent location in external memory.
The errant DMA read returns zeros.
3ABC
AC bias count status.
0 – AC bias transition counter has not decremented to zero, or API is programmed to all
zeros.
1 – AC bias transition counter has decremented to zero, indicating that the L_BIAS pin has
transitioned the number of times specified by the API control bit field. Counter is reloaded
with the value in API but is disabled until the user clears ABC.
4 IOL
Input FIFO overrun lower panel status.
0 – Input FIFO for the lower panel display has not overrun.
1 – DMA attempted to place data into the input FIFO for the lower panel after it has been
filled.
5IUL
Input FIFO underrun lower panel status.
0 – Input FIFO for the lower panel display has not underrun.
1 – DMA not supplying data to input FIFO for the lower panel at a sufficient rate. FIFO has
completely emptied; pixel unpacking logic has attempted to take added data from the FIFO.