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SA-1110 Developer’s Manual 161
Memory and PC-Card Control Module
Figure 10-9. DRAM/SDRAM CBR Refresh Cycle
10.5.7 DRAM/SDRAM Self-Refresh in Sleep Mode
The SA-1110 puts the DRAM into the self-refresh state prior to entering sleep mode by driving all
nCAS/DQM low, then driving all nRAS/nSDCS low (just as for a normal CBR refresh cycle), and
maintaining them low while core power (VDD) and clocks are turned off. The SDRAM
self-refresh command (SLFRSH) differs from auto-refresh command (CBR) in that SLFRSH
drives the SDCKE[1:0] signals low. They will continue to be held low throughout sleep.
SDCLK[2:0] stop running throughout sleep: SDCLK[2:1] are held high; SDCLK 0 is held low if
auto-power-down is enabled, or held high if auto-power-down is disabled.
See Section 9.5 for details on how to bring DRAM out of self-refresh mode. See Section 10.5.5 and
section 10.2.1 on page 125 for details on how to bring SDRAM out of self-refresh mode. An access
to a DRAM bank while the DRAM interface is in self-refresh mode has undefined results, but the
DRAM remains in self-refresh.
A6638-01
CPU Clock
SDCLK
Memory
Clock
SDCKE
command
DRA13-12
DRA11
DRA10
DRA9-0
nSDRAS
nRAS/nSDCS
nSDCAS
nCAS/DQM
PALL CBR ACT
SDRAM only
nWE
Bank
Row
Row
Row
1234567891011121314151617181920
TRASR+1