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SA-1110 Developer’s Manual 249
Peripheral Control Module
11.7.11.1 LCD Disable Done Flag (LDD) (read/write, maskable interrupt)
The LCD disable done (LDD) status is set after the LCD has been disabled and the frame that is
active finishes being output to the LCD’s data pins. When the LCD is disabled by clearing the LCD
enable bit
(LEN= 0 → 1) in LCCR0, the LCD allows the current frame to complete before it is
disabled. After the last set of pixels is clocked out onto the LCD’s data pins by the pixel clock, the
LCD is disabled, LDD is set, and an interrupt request is made to the interrupt controller if it is
unmasked (LDM=0). This interrupt is useful to allow an orderly shutdown of the LCD controller
before the user places the SA-1110 into sleep mode.
11.7.11.2 Base Address Update Flag (BAU) (read-only, maskable interrupt)
The base address update status (BAU) is a read/write status bit that is set after the contents of the
DMA base address register 1 are transferred to the DMA current Address register 1 and is cleared
when it is written to a 1. The value in the base address register is transferred to the current address
register when the LCD is first enabled by writing a 1 to LEN
(LEN= 0 → 1) and when the current
address pointer equals the end address value calculated by the LCD controller. When BAU is set,
an interrupt request is made to the interrupt controller if it is unmasked (BAM = 0). This interrupt
allows the user to program the DMA with a new base address value to alternate between two or
more frame buffer locations. When dual-panel mode is enabled (SDS=1), both DMA channels are
enabled, and BAU is set only after both channels' base address registers are transferred to their
corresponding current address registers (1 and 2).
11.7.11.3 Bus Error Status (BER) (read/write, maskable interrupt)
The bus error status (BER) bit is set when a DMA transfer causes a bus error to occur on the ARM
system bus. A bus error is signalled when the DMA controller attempts to access a reserved or
nonexistent memory space. When this occurs, the SA-1110’s memory controller returns zeros for
the read. It asserts the bus error signal to the LCD’s DMA, which in turn, causes the BER bit to be
set and an interrupt request is made to the interrupt controller if it is unmasked (ERM = 0). The
DMA is not disabled as a result of the bus error and operation continues as normal. If a DMA
access causes a bus error, zeros are returned by the memory controller, which causes a palette entry
to be filled with zeros (highest intensity color or black), or if pixel data is being DMAed, the LCD
accesses the first location of the palette RAM one or more times.
11.7.11.4 AC Bias Count Status (ABC) (read/write, nonmaskable interrupt)
The ac bias count status (ABC) bit it set each time the ac bias pin (L_BIAS) transitions a particular
number of times as specified by the ac bias pin transitions per interrupt (API) field in LCCR3. If
API is programmed with a nonzero value, a counter is loaded with the value in API and is
decremented each time the L_BIAS pin reverses state. When the counter reaches zero, the ABC bit
is set, which signals an interrupt request to the interrupt controller. The counter reloads using the
value in API, but does not start to decrement again until ABC is cleared by the user.
11.7.11.5 Input FIFO Overrun Lower Panel Status (IOL) (read/write, maskable
interrupt)
The input FIFO overrun lower panel status (IOL) bit is set when the LCD’s DMA channel 2
attempts to place data into the lower panel’s input FIFO after it has been completely filled. It is
cleared by writing a 1 to the bit. This bit is used only in dual-panel mode (SDS=1). When this bit is
set, an interrupt request is made to the interrupt controller if it is unmasked (ERM=0).