Filter
Top Products
SA-1110 Developer’s Manual 5
8.3 Driving Intel® StrongARM SA-1110 Crystal Pins from an External Source................................71
8.4 Clocking During Test...................................................................................................................72
9 System Control Module
9.1 General-Purpose I/O...................................................................................................................73
9.1.1 GPIO Register Definitions ..............................................................................................74
9.1.1.1 GPIO Pin-Level Register (GPLR).................................................................... 75
9.1.1.2 GPIO Pin Direction Register (GPDR).............................................................. 76
9.1.1.3 GPIO Pin Output Set Register (GPSR) and Pin Output
Clear Register (GPCR) ................................................................................... 77
9.1.1.4 GPIO Rising-Edge Detect Register (GRER) and
Falling-Edge Detect Register (GFER)............................................................. 78
9.1.1.5 GPIO Edge Detect Status Register (GEDR)................................................... 79
9.1.1.6 GPIO Alternate Function Register (GAFR) ..................................................... 80
9.1.2 GPIO Alternate Functions...............................................................................................81
9.1.2.1 3.6864 MHz Option for GP 27 Alternate Output Function............................... 82
9.1.3 GPIO Register Locations................................................................................................82
9.2 Interrupt Controller ......................................................................................................................83
9.2.1 Interrupt Controller Register Definitions .........................................................................84
9.2.1.1 Interrupt Controller Pending Register (ICPR).................................................. 84
9.2.1.2 Interrupt Controller IRQ Pending Register (ICIP) and
FIQ Pending Register (ICFP).......................................................................... 86
9.2.1.3 Interrupt Controller Mask Register (ICMR)...................................................... 87
9.2.1.4 Interrupt Controller Level Register (ICLR)....................................................... 88
9.2.1.5 Interrupt Controller Control Register (ICCR)................................................... 89
9.2.2 Interrupt Controller Register Locations...........................................................................90
9.3 Real-Time Clock..........................................................................................................................90
9.3.1 RTC Counter Register (RCNR) ......................................................................................90
9.3.2 RTC Alarm Register (RTAR) ..........................................................................................91
9.3.3 RTC Status Register (RTSR) .........................................................................................91
9.3.4 RTC Trim Register (RTTR).............................................................................................93
9.3.5 Trim Procedure...............................................................................................................93
9.3.5.1 Oscillator Frequency Calibration..................................................................... 93
9.3.5.2 RTTR Value Calculations................................................................................ 94
9.3.6 Real-Time Clock Register Locations ..............................................................................95
9.4 Operating System Timer .............................................................................................................95
9.4.1 OS Timer Count Register (OSCR) .................................................................................96
9.4.2 OS Timer Match Registers 0–3 (OSMR 0, OSMR 1, OSMR 2, OSMR 3)......................96
9.4.3 OS Timer Watchdog Match Enable Register (OWER)...................................................96
9.4.4 OS Timer Status Register (OSSR).................................................................................97
9.4.5 OS Timer Interrupt Enable Register (OIER)...................................................................98
9.4.6 Watchdog Timer .............................................................................................................98
9.4.7 OS Timer Register Locations .........................................................................................99
9.5 Power Manager..........................................................................................................................99
9.5.1 Run Mode.......................................................................................................................99
9.5.2 Idle Mode........................................................................................................................99
9.5.2.1 Entering Idle Mode........................................................................................ 100
9.5.2.2 Exiting Idle Mode........................................................................................... 100
9.5.3 Sleep Mode ..................................................................................................................101